Speaker
Description
Static random-access memories (SRAMs) are commonly used in high access-rate applications due to their fast operation and compatibility with CMOS logic. Nevertheless, their significant power consumption and limited storage density render them impractical, particularly for cryogenic applications where power constraints hinder scalability. In contrast, dynamic random-access memories (DRAMs) can address the issue of density by storing data as a charge on a capacitor (or parasitic capacitor), requiring fewer transistors per memory cell. However, the need for frequent refreshing to overcome leakages on the charge-storing node leads to a significant power consumption. It is widely recognized that at cryogenic temperatures (CT), the subthreshold slope (SS) decreases, while the threshold voltage of CMOS increases, aiding in reducing subthreshold leakage. Additionally, the mismatch in different transistor parameters also increases. Recently, there has been a growing interest in determining whether DRAMs can outperform SRAMs at CTs based on criteria such as power consumption, retention time, and latency or access time. Known for their density benefits, DRAMs have been observed to surpass SRAMs at 4 K due to the significant decrease in leakage current. This improvement is attributed to the inherent nature of DRAM cells, which rely on charge storage mechanisms rather than continuously powered latches like SRAMs. At lower temperatures, the reduction in thermal energy suppresses carrier generation, resulting in decreased leakage currents in DRAM cells. Consequently, DRAMs exhibit better energy efficiency and greater reliability compared to SRAMs in cryogenic settings. However, one notable limitation is the mismatch in retention time among DRAM cells operating at CTs. To date, there have been no studies reporting on the impact of mismatch on DRAM performance as it is cooled down to 4 K. This study delves into this effect by examining the mismatch through an array of 9x10 DRAM cells. The FPGA generates the read/write/refresh sequence for the DRAMs die mounted in a Lake shore probe station. When the read signal is activated, it triggers an internal counter that stops once the DRAM output falls below a set threshold (600 mV in this particular study). The supplied digital voltage ranges from 1 V to 1.4 V to examine how it affects the retention time of the cells and the mismatch across the entire array. Due to the anticipated rise in the threshold voltage at 4 K, the operational cells start functioning at an elevated supply voltage of 1.2 V compared to room temperature (RT) operation. The decrease in subthreshold leakages at 4 K and the increase in the threshold voltage of the transistors are two conflicting mechanisms that can influence whether the retention times will increase as the temperature drops or not. This effect becomes noticeable when examining the data collected for three different VDD values: 1.2 V, 1.3 V, and 1.4 V at two temperatures, 293 K and 4 K. At 4 K, the retention times decreased by half when supplied at 1.2 V, while at 1.3 V, there was a 200 % increase in retention times, and at 1.4 V, the retention times increased by approximately 225 %. Another parameter examined in this research is the mismatch not only at the pixel level but also among the various cells of the 90 pixel array. The former is assessed by conducting numerous acquisitions and deriving the standard deviation () of the normal distribution of retention times for the same cell. The results show that at RT the deviation is 0.28 ms independently of the supply voltage value. After the cooling process, there is an increase in mismatch among different pixels by 100 %, 25 %, and 100 % at 1.2 V, 1.3 V, and 1.4 V, respectively. This data offers valuable insights into the retention time characteristics of DRAMs and the impact of cooling on mismatch, which is essential for designers, particularly those considering the use of memory cells in cryogenic applications like quantum computing or SNSPD arrays that require operation around 4 K.
| Submitters Country | Switzerland |
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