11–13 Jun 2024
CERN
Europe/Zurich timezone
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FPGA firmware design and verification for the ATLAS Liquid Argon Calorimeter trigger processor

12 Jun 2024, 10:30
15m
30/7-018 - Kjell Johnsen Auditorium (CERN)

30/7-018 - Kjell Johnsen Auditorium

CERN

190
Show room on map
Solutions to everyday digital design problems Solutions to everyday digital design problems

Speakers

Lucca Oliveira Facio Viccini (CERN) Marcos Vinicius Silva Oliveira (Brookhaven National Laboratory (US)) Melissa Aguiar (Federal University of Juiz de Fora (BR))

Description

Firmware design is a major challenge in LHC experiment upgrades, often leading to significant project delays. While non configurable systems were immediately operational, recent experiences show firmware and hardware readiness can take years. This underscores the need for innovative methods to speed up firmware design and deployment. This study utilizes advanced firmware design techniques, like High-Level Synthesis (HLS), for the ATLAS Liquid Argon Calorimeter trigger processor. HLS simplifies the design process by focusing on essential functions rather than intricate hardware details such as clock networks or signal interfaces. This method allows for easy trade-offs between latency and area, essential for optimizing firmware performance. It enhances firmware maintenance, latency, logic area usage, and timing accuracy. The HLS application has the potential to streamline firmware design, reducing project delays, and increasing efficiency in large-scale experiments like the LHC upgrades.

Talk's Q&A End of talk
Talk duration 10'+5' (very short, not recommended)
Will you be able to present in person? Yes

Primary author

Melissa Aguiar (Federal University of Juiz de Fora (BR))

Co-authors

Lucca Oliveira Facio Viccini (CERN) Marcos Vinicius Silva Oliveira (Brookhaven National Laboratory (US))

Presentation materials