1st FPGA Developers' Forum (FDF) meeting

Artificial Intelligence workflows for FPGA & SoC using a Deep Learning Processor

12 Jun 2024, 11:45

30m

30/7-018 - Kjell Johnsen Auditorium (CERN)

Algorithm implementation in HDL and HLS Algorithm implementation

Speaker

Stephan van Beek (MathWorks)

Description

Artificial intelligence (AI) is everywhere. Automated image analysis, autonomous driving, industrial inspection, there are many applications today that could benefit from AI. Deep Learning is the most successful solution for image-based object classification, and for most practical applications it requires performant platforms like FPGAs and SoCs.

Designing AI for embedded devices such as FPGAs and SoCs is challenging because of resource constraints, the complexity of programming in Verilog or VHDL, and the hardware expertise needed for prototyping on an FPGA or SoC.

In this presentation I will explain, how to:
- Prototype and deploy Deep Learning-based vision applications using a Deep Learning Processor (DLP).
- Analyze profiling metrics and use compression methods like quantization and pruning to improve performance.
- Optimize the Deep Learning Processor configuration for the chosen AI models.

Presentation materials

Artificial Intelligence workflows for FPGA and SoC using a Deep Learning Processor.pdf

Artificial Intelligence workflows for FPGA and SoC using a Deep Learning Processor.pptx