11–13 Jun 2024
CERN
Europe/Zurich timezone
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Resource-efficient FPGA implementation of a channelization stage for superconducting quantum detectors DAQ systems

12 Jun 2024, 15:05
20m
30/7-018 - Kjell Johnsen Auditorium (CERN)

30/7-018 - Kjell Johnsen Auditorium

CERN

190
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Algorithm implementation in HDL and HLS Algorithm implementation

Speaker

Timo Muscheid

Description

Modern experiments in particle physics and astrophysics rely on quantum detectors for superior energy resolutions. These detectors require specialized readout electronics employing frequency division multiplexing. Operational challenges include managing a high number of tones in the transmission lines, which further complicates the FPGA firmware. For instance, the ECHo experiment plans to operate ~12,000 MMCs to study the upper limit of electron neutrino mass. Similarly, BULLKID-DM will employ ~3,000 KIDs to search for dark matter. Room-temperature electronics handle digital synthesis of microwave tones and real-time data processing. A polyphase channelizer (PPC) and digital downconversion (DDC) facilitate sub-band separation and variable tone filtering. This FPGA-based channelization stage is adaptable to various experiments. Methods for modifying PPC and DDC for different detector parameters are also discussed, along with characterization techniques for assessing their performance.

Talk's Q&A During the talk
Talk duration 20'+10'
Will you be able to present in person? Yes

Authors

Timo Muscheid Luis Ardila-Perez (Institute for Data Processing and Electronics (IPE), Karlsruhe Institute of Technology (KIT)) Oliver Sander (KIT - Karlsruhe Institute of Technology (DE))

Presentation materials