1st FPGA Developers' Forum (FDF) meeting

Session

Sharable HDL Cores

11 Jun 2024, 15:40

30/7-018 - Kjell Johnsen Auditorium (CERN)

Conveners

Sharable HDL Cores

• Francesco Gonnella (University of Birmingham (GB))
• Mathieu Saccani (CERN)

15. Convenient and reliable clock domain crossings, using scoped constraints and reusable blocks

Lukas Vik (Freelance)

11/06/2024, 15:40

Sharable HDL cores

Despite being used regularly by all FPGA designers, very few people know how to properly and reliably constrain a clock domain crossing (CDC). Timing constraints are indeed one of the hardest parts of FPGA design. It is an elusive art that is impossible to google and impossible to verify.

In this session we will discuss a few common CDC topologies. Analyze them, discuss some common...

1. COLIBRI: Towards a CERN-wide common cores library

Alberto Perro (Universite d'Aix-Marseille III (FR))

11/06/2024, 16:20

Sharable HDL cores

In modern Data Acquisition (DAQ) gateware, developers use many basic parts to make custom features. These parts come from vendors or are made by developers themselves. This often leads to a fragmented codebase difficult to test, integrate, and use with different tools. To fix this, a new open-source core library has been made.
This library is a collection of commonly used cores and blocks...

32. CERN control group cores and tools

Tristan Gingold (CERN)

11/06/2024, 16:50

Sharable HDL cores

The CERN control group (in particular the BE-CEM-EDL section, previously BE-CO-HT) is at the origin of the White Rabbit technology. But in addition to this well known project, the section has also developed a set of generic cores (named general-cores), a tool to automatically build project for simulators and synthesizers starting from a python description (hdlmake), as well as a tool to...

21. Fast Monitoring of FPGA algorithms using SpyBuffers

Iacopo Longarini (University of California Irvine (US))

11/06/2024, 17:20

Sharable HDL cores

The development, testing and operation of FPGA algorithms require the implementation
of flexible and efficient real-time monitoring. This can be achieved
via the insertion of dedicated buffers between the logical blocks of the FPGA
firmware. These buffers are implemented in the firmware to spy the dataflow
between the internal blocks (Spybuffers). They must provide configurable size
and...

12. The BondMachine Project

Mirko Mariotti (Universita e INFN, Perugia (IT)), Mirko Mariotti (Universita e INFN, Perugia (IT))

11/06/2024, 17:50

Sharable HDL cores

Since 2017 we started R&D on framework development for co-designing (HW/SW) computational systems, targeting mainly FPGAs. The main innovation of the project, named BondMachine (BM), is the creation of a new type of architecture, dynamically adapted to the specific problem. The framework contains a set of tools to manipulate the architectures, spanning from the creation to the simulation and...