25–29 May 2026
Chulalongkorn University
Asia/Bangkok timezone

Designing a Heterogeneous Computing Architecture for Level-1 Data Scouting in CMS at the HL-LHC

Not scheduled
1m
Chulalongkorn University

Chulalongkorn University

Poster Presentation Track 2 - Online and real-time computing Poster

Speaker

Giovanni Zago (Universita e INFN, Padova (IT))

Description

The Level-1 Data Scouting (L1DS) system introduces a new real-time data acquisition and processing path in CMS that captures information reconstructed by the Level-1 Trigger at the full 40 MHz collision rate, without any preselection. For the HL-LHC era, the Level-1 Trigger will undergo a major architectural evolution, delivering significantly richer and higher-quality reconstructed physics objects. This shift toward near-offline reconstruction at the trigger level introduces substantially increased computational requirements for continuous 40 MHz acquisition. To address these constraints, we explore a heterogeneous computing system for L1DS integrating multiple types of hardware accelerators. AMD Versal adaptive SoC platforms are evaluated for offloading event selection workloads using a combined FPGA and AI Engines design, demonstrating efficient low-latency processing even for non-ML algorithms. In parallel, NVIDIA GPUs are also benchmarked for more demanding reconstruction tasks, including real-time clustering and transformer-based ML model inference. We present performance measurements, data movement strategies, and scaling behavior under representative L1DS configurations. The results demonstrate the feasibility and limitations of heterogeneous acceleration for sustained 40 MHz operation and provide design guidance for deploying and optimizing L1DS computing during HL-LHC data taking.

Author

Giovanni Zago (Universita e INFN, Padova (IT))

Presentation materials

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