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Alexander Daum (p2l2)5/27/26, 7:00 PMSharable HDL coresPoster
When developing FPGA applications, accessing real data can be a crucial help during debugging and algorithm development.
However, especially in applications with high data rates, it is often difficult to transfer data fast enough or buffer enough data.This talk presents RoCE-Stream, an FPGA core, built upon the open-source fpga-network-stack, to transfer data from any AXI-Stream source to...
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Georgios Flengas (CERN)5/27/26, 7:01 PMHDL development toolsPoster
This talk presents a CI-driven pipeline for FPGA machine-learning deployment optimized for rapid experimentation and reproducible comparison. The workflow automates ONNX/QONNX conversion, hls4ml project generation, build orchestration, and validation, allowing engineers to configure key design parameters directly from the CI interface for each experiment run. The main contribution is unified...
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Mr Janik Witzig (Ostschweizer Fachhochschule), Lukas Leuenberger (Ostschweizer Fachhochschule)5/27/26, 7:02 PMHDL development toolsPoster
XiBIF, short for Xilinx Board Interface, is an open-source FPGA development framework that combines a Python-based tool flow with a ready-made hardware platform featuring built-in communication over Ethernet.
The tool allows for quick project creation and ideation. It supports fast project setup, automated Vivado/Vitis build steps, and direct host-to-FPGA communication. Out-of-the-box,...
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Louis Ledoux (INSA, INRIA)5/27/26, 7:03 PMHDL development toolsPoster
This work presents an end to end compilation flow that lowers high level machine learning and DSP kernels to explicit combinational and pipelined datapaths targeting FPGA and reconfigurable dataflow architectures. Arithmetic is treated as a multi level
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concern, progressively exposing mathematical structure, numeric intent, and hardware organization from tensor programs to synthesizable RTL.... -
Volker Urban (Ingenieurbüro Dipl.-Ing. Volker Urban)5/27/26, 7:04 PMSolutions to everyday digital design problemsPoster
The emulation of classic CPUs from the 1980s, such as the Motorola MC680xx series, is currently achieved through:
• (Full) software emulation running on a RISC processor
• (Full) hardware emulation (RT-level) on a programmable logic device (i.e. FPGA)With the advent of SoC-FPGAs like the AMD Zynq, which combine CPU and FPGA logic in a single device, a platform is available for a...
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91. Benchmarking Neural Network Inference on Versal ACAP AI Engines for Real-Time Detector AlignmentHaider Abidi (Brookhaven National Laboratory (US))5/27/26, 7:05 PMAlgorithm implementation in HDL and HLSPoster
Real-time detector alignment is critical for minimizing systematic biases in reconstructed trajectories. Standard calibration methods are often computationally expensive and struggle with latency in dynamic conditions. We propose a solution using a lightweight neural network with hierarchical subset solvers, optimized for the AMD Versal ACAP.
Our implementation maximizes heterogeneous...
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Marwin Kirchhofs5/27/26, 7:06 PMAlgorithm implementation in HDL and HLSPoster
Simulating quantum state vectors is constrained by the exponential scaling in computation complexity and data structure size, but well suited for parallel execution. However, existing methods struggle with fully leveraging DDR-based accelerators for the task. Furthermore, proposed FPGA designs lack "arbitrary operation" capability and scalability. This work introduces "labeled-random" state...
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Inès Winandy (ENAC)5/27/26, 7:07 PMHDL development toolsPoster
Aerospace systems are real-time critical, meaning they must meet strict timing and traceability constraints to avoid material damage and injuries. Systems present in particle accelerators may face the same constraints. FPGAs can be reconfigured and have the advantage that timing constraints can be easily guaranteed. Some HLS tools produce RTL code for configuring FPGAs from dataflow...
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Patrick Urban (Cologne Chip AG)5/27/26, 7:08 PMSolutions to everyday digital design problemsPoster
Radiation effects are a critical concern for electronic systems operating in space, high-energy physics experiments, and other radiation-prone environments. Ensuring FPGA reliability in such conditions requires rigorous qualification methodologies to assess susceptibility to radiation-induced failures, including Single Event Latchup or Upset (SEL, SEU) and Total Ionizing Dose (TID)...
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Marcel Marques Boonen (Max Planck Society (DE))5/27/26, 7:09 PMAlgorithm implementation in HDL and HLSPoster
The L0MDT muon track finder algorithm will be implemented on the MDT Trigger Processor (MDTTP) ATCA board, featuring an AMD xcvu13p FPGA. To validate this, we propose using a 2020 demonstrator board (equipped with two AMD XCZU11EG FPGAs and three DDR4 modules) to emulate data flow.The demonstrator will simulate incoming signals from L0Muon systems (Front-End and Sector Logic) and internal...
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Frederik Schmitt (Karlsruhe Institut of Technology)5/27/26, 7:10 PMSolutions to everyday digital design problemsPoster
The IceCube Neutrino Observatory is a particle detector located at the South Pole, consisting of two components: a cubic-kilometer in-ice neutrino detector, and the IceTop surface array for high-energy cosmic rays.
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For the proposed next generation neutrino observatory IceCube-Gen2, the surface instrumentation will be enhanced by an array of scintillators and radio antennas organized in local... -
Pradeep Kumar Mohanty (NIT Rourkela)5/27/26, 7:11 PMAlgorithm implementation in HDL and HLSPoster
Lightweight cryptographic primitives are applied more and more in rugged FPGA systems with low resources where the security has to be weighed against the very strict limits of area, power, and latency. Even though the specifications have been around for a while, the efficient and secure hardware implementation is still a big challenge.
The above mentioned talk will tell about practical...
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Alexander Novikov (University of Delaware)5/27/26, 7:12 PMSolutions to everyday digital design problemsPoster
Radio Frequency System-on-Chip (RFSoC) is a powerful technology for various astroparticle physics experiments, in particular the ones using radio signals as the main detection channel. This poster will present the design of the RFSoC-based DAQ for the Radio Instrument of the POEMMA (Probe Of Extreme Multi-Messenger Astrophysics) Balloon with Radio (PBR) – a Super-Pressure Balloon experiment...
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Mr Bruno Fernandes (Eur.XFEL (European XFEL))5/27/26, 7:13 PMSolutions to everyday digital design problemsPoster
Instruments at the European X-Ray Free Electron Laser (EuXFEL) receive femtosecond coherent X-ray pulses with 220 nanoseconds spacing in burst up to 3600 pulses every 100 ms.
As experimental demands increase, close interaction with users has led to the development of highly customized firmware and FPGA-based processing solutions. Leveraging our expertise, we plan to accelerate established...
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Ms Handan YILMAZ (istanbul technical University)5/27/26, 7:14 PM1HDL verification and simulation toolsPoster
FPGA firmware for radiation detector readout is often validated with idealized inputs that miss pile-up, baseline drift, statistical fluctuations and mixed fields. We present a simulation-driven workflow to generate realistic digitized waveforms using Geant4 and to reuse them for FPGA verification. Starting from energy deposition, we model detector response and electronics effects (shaping,...
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Liqing Qin (Heidelberg Ion Beam Therapy Centre)5/27/26, 7:15 PMAlgorithm implementation in HDL and HLSPoster
The scintillating fiber and photodiode array–based beam profile monitor is being developed for the Heidelberg Ion Beam Therapy Centre as a next-generation device for ion beam therapy. The prototype acquires 320 channels of 16-bit data at a frame rate of 100µs on an Intel Max10 FPGA. The main challenge is to achieve fully hardware-based, low-latency beam reconstruction within the limited...
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Zhiqiang Que (University of Bristol)5/27/26, 7:16 PMAlgorithm implementation in HDL and HLSPoster
Graph Neural Networks (GNNs), especially Interaction Networks, achieve strong jet tagging performance at the CERN HL-LHC but are difficult to deploy on FPGAs due to high complexity and irregular memory access under strict latency constraints. We propose JEDI-linear, a GNN with linear complexity that removes explicit pairwise interactions using shared transformations and global aggregation. We...
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Javier Galindo Guarch (Aragon Institute of Technology Itainnova (ES))5/27/26, 7:17 PMAlgorithm implementation in HDL and HLSPoster
We present an IP core for arbitrary and real-time variable sampling rate conversion in data-stream processing. The IP solves a common design challenge in CERN synchrotrons: maintaining a fixed ADC/FPGA system clock (White Rabbit based), preferred for timing closure and clock-domain robustness, while processing data at a rate proportional to the beam revolution frequency, the so-called bunch...
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Luca Russo (Universita e INFN, Perugia (IT))5/27/26, 7:18 PMAlgorithm implementation in HDL and HLSPoster
The Streaming Median Algorithm (SMA) implements an heap-sorting algorithm to compute median in FPGA exploiting its concurrent architecture. SMA consists of 2 heaps: max-heap sorts the lower values while min-heap the upper values. Each new 16-bit word is inserted in either of the 2 roots, and a rebalancing follows each insertion. Eventually, root of max-heap represents the maximum of the lower...
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David Ganz (ZHAW)5/27/26, 7:19 PMAlgorithm implementation in HDL and HLSPoster
We present a solution for AI inference on heterogeneous AI accelerators with some acceleration microkernels implemented in an FPGA. The solution is part of a software framework for AI execution orchestration that can be optimised for latency & power on constrained embedded systems. This orchestration can trigger AI execution on a diversity of AI accelerators, for example GPUs but also NEON/DSP...
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Yair Linn (TRIUMF)5/27/26, 7:20 PMHDL development toolsPoster
We discuss and contrast SVN vs. GIT for FPGA HDL development. Hierarchical designs with multiple repositories are common for large FPGA projects. SVN:Externals provides native hierarchical support with precise submodule references, requiring no plugins or scripting. GIT Submodules are cumbersome by contrast and require careful cross-repository coordination. More critically, GIT clones entire...
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Augusto Fraga Giachero (CNPEM / LNLS)5/27/26, 7:21 PMHDL verification and simulation toolsPoster
VHPIDIRECT is a simple API originally implemented in GHDL and later adopted by NVC that allows VHDL functions and procedures to be implemented in any language that compiles into native code and exposes a C ABI calling convention. As an example of its capabilities, this work presents a VHDL package that has been developed to write an HDF5 file containing frame data decoded from Timepix4 raw...
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Maryam Eslami (Ruhr-Universität Bochum)5/27/26, 7:22 PMSolutions to everyday digital design problemsPoster
Deep neural networks (DNNs) have been applied across diverse domains, including safety-critical applications. Past studies indicate that DNNs are very sensitive to changes in weights and activations due to uneven bit-weight distribution in standard number formats like fixed points, which can cause significant output accuracy fluctuations. To address this issue, we introduce a new data type...
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Nicolo Ghielmetti (CERN)5/27/26, 7:23 PMAlgorithm implementation in HDL and HLSPoster
Portable, reproducible FPGA ML inference benefits from open-source, vendor-agnostic HLS flows. We present a new hls4ml backend for PandA-Bambu, an open-source HLS tool that generates RTL from C/C++. The backend adds Bambu-specific writer integration, Bambu-compatible datatypes, and pragma/code-generation support for synthesis and simulation, together with template/numerical variants (e.g.,...
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Mr Tommaso Fellegara (Politecnico di Milano)5/27/26, 7:24 PMHDL development toolsPoster
This talk presents Bambu, an open-source research and development platform for high-level synthesis (HLS). Bambu (https://github.com/ferrandi/PandA-bambu) supports rapid experimentation across high-level verification and debugging, FPGA/ASIC design, design-flow space exploration, and parallel accelerator generation. It supports standard C/C++, enabling the EDA community to prototype new...
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Paula Martinez Suarez (CERN)5/27/26, 7:25 PMAlgorithm implementation in HDL and HLSPoster
The LHC can provide up to 40 MHz of proton-proton collisions to the ATLAS experiment, which must be filtered in real time down to 100 kHz in order to meet the readout constraints. This task is performed by the Level-1 Trigger, which uses FPGA-based hardware to select the most relevant events within a few microseconds. Traditionally, Level-1 Trigger algorithms have been designed to target a set...
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Lorenzo Borella (Universita e INFN, Padova (IT))5/27/26, 7:26 PMAlgorithm implementation in HDL and HLSPoster
This work presents an FPGA-based implementation of the Elias algorithm for deterministic entropy extraction. The input consists of strongly biased binary sequences generated by a single-photon detector, forming a true Quantum Random Number Generator (QRNG). Assuming the raw bits are independent and identically distributed with unknown bias, the Elias extractor deterministically converts this...
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Adam Lee Barcock (Science and Technology Facilities Council STFC (GB))5/27/26, 7:27 PMHDL development toolsPoster
The Firmware Development Kit (FDK) is a software application that simplifies HDL version management, build tool project creation, and build flow management for FPGA. The software is used by staff in the Technology Department at STFC and is now being commercialised. The FDK provides the following functionality:
- Simplified build tool project creation. The FDK parser reads the HDL to...
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Mr Allan Borgato (LNLS)5/27/26, 7:28 PMSolutions to everyday digital design problemsPoster
Closing timing constraints becomes increasingly challenging as FPGA solutions grow in area utilization. This work presents a frame-rate enhancement technique using FPGA frame buffering for SIRIUS Mobipix 15D, a Medipix3RX-based area detector, generating larger composite images for transmission over a camera serial interface to a System-on-Module (SoM), thereby increasing the effective X-ray...
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Matthew Schiller (National Radio Astronomy Observatory (USA))Algorithm implementation in HDL and HLSPoster
In communication systems and Radio Telescopes a common receiver implementation is a "Zero-IF" receive architecture. When this architecture is combined with a high bandwidth receiver, correcting for I/Q balence becomes non-trivial as the quadrature mixer is rarely ideal over high bandwidth. Further, in radio astronomy, which utlizes receivers spread out over large distances, it is useful to...
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