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1:00 PM
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Conference Registration
(until 2:00 PM)
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2:00 PM
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Introduction
-Dr
Francesco Gonnella
(University of Birmingham (GB))
(until 3:00 PM)
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2:00 PM
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Welcome to FDF26
-
Davide Cieri
(Max Planck Society (DE))
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2:10 PM
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What Star Trek can teach us about using AI in FPGA design
- Mr
Adam Taylor
(Adiuvo Engineering)
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3:00 PM
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Sponsor Presentations
(until 3:45 PM)
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3:00 PM
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Altera
-
Christian Faerber
(Altera)
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3:03 PM
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AMD
-
Thilo Ohlemueller
(AMD)
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3:06 PM
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CAEN
-
Luca Colombini
(CAEN)
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3:09 PM
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CAST
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Calliope-Louisa Sotiropoulou
(CAST)
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3:12 PM
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Efinix
- Mr
Fabian Heinrici
(Efinix)
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3:15 PM
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iWave
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Sharath Kumar
(iWave)
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3:18 PM
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Knowledge Resources
-
Bruno Monteiro
(Knowledge Resources GmbH)
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3:21 PM
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Lattice Semiconductor
-
Hardik Shah
(Lattice)
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3:24 PM
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Microchip
- Mr
Jens Huettemann
(Microchip Technology Munich GmbH)
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3:27 PM
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NanoXplore
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JEAN LOUIS FRIGOUL
(NANOXPLORE)
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3:30 PM
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PLC2
-
Patrick Lehmann
(PLC2)
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3:33 PM
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ProDesign
-
Stefan Rooseboom
(ProDesign)
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3:36 PM
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Samtec
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Veronique Branca
(Samtec)
Neil Potter
(Samtec)
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3:39 PM
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Techway
-
Romain Larousse
(Techway)
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3:42 PM
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Trenz Electronic
-
Martin Rohrmüller
(Trenz Electronic)
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3:45 PM
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--- Tea Break ---
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4:15 PM
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Sharable HDL cores
-
Filiberto Bonini
(CERN)
(until 6:30 PM)
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4:15 PM
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Scalable and lightweight RoCEv2 TX FPGA IP core
-
Gabriele Bortolato
(Universita e INFN, Padova (IT))
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4:45 PM
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The PoC-Library - Free and Open-Source VHDL IP Core Library
-
Patrick Lehmann
(PLC2)
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5:25 PM
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NDK framework: Deep-Diving into High-Throughput Network Monitoring Pipelines
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Daniel Kondys
(CESNET)
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6:00 PM
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USB implementation with GateMate FPGA
-
Anton Kuzmin
(gmm7550)
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6:30 PM
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--- Group Photo ---
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7:00 PM
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Poster Session and Welcome Reception
(until 8:00 PM)
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7:00 PM
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RoCE-Stream -- offloading (debug) data over 100Gbit RoCE RDMA
-
Alexander Daum
(p2l2)
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7:01 PM
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CI-Driven FPGA ML Experimentation: Unified Results from HLS, Implementation, and On-Hardware Testing
-
Georgios Flengas
(CERN)
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7:02 PM
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XiBIF: A Python tool and hardware platform for streamlined FPGA development
- Mr
Janik Witzig
(Ostschweizer Fachhochschule)
Lukas Leuenberger
(Ostschweizer Fachhochschule)
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7:03 PM
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Progressive Arithmetic Optimizations : Tensor and DSP Kernels to Synthesizable Datapaths
-
Louis Ledoux
(INSA, INRIA)
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7:04 PM
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Emulation of classic CPUs - a SoC-centric hybrid approach
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Volker Urban
(Ingenieurbüro Dipl.-Ing. Volker Urban)
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7:05 PM
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Benchmarking Neural Network Inference on Versal ACAP AI Engines for Real-Time Detector Alignment
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Haider Abidi
(Brookhaven National Laboratory (US))
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7:06 PM
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Leveraging HBM for accelerating arbitrary Quantum Simulation on AMD Alveo platforms
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Marwin Kirchhofs
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7:07 PM
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Towards a predictable toolchain dedicated to the generation of FPGA circuits for control algorithms
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Inès Winandy
(ENAC)
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7:08 PM
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Qualifying FPGAs for Radiation-Tolerant Applications
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Patrick Urban
(Cologne Chip AG)
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7:09 PM
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An Hardware Emulator for the ATLAS Phase-II L0MDT Trigger System
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Marcel Marques Boonen
(Max Planck Society (DE))
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7:10 PM
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Deep Memory for the Data Acquisition of the IceCube-Gen2 Surface Array
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Frederik Schmitt
(Karlsruhe Institut of Technology)
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7:11 PM
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Practical Implementation of Lightweight Cryptography on FPGAs: Design Trade-offs, Side-Channel Considerations, and Integration Lessons
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Pradeep Kumar Mohanty
(NIT Rourkela)
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7:12 PM
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POEMMA Balloon with Radio experiment as a use case for RFSoC in Astroparticle Physics
-
Alexander Novikov
(University of Delaware)
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7:13 PM
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Transitioning to Modern FPGA Architectures in a High-Throughput Research Facility
- Mr
Bruno Fernandes
(Eur.XFEL (European XFEL))
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7:14 PM
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Geant4-driven realistic waveform generation for FPGA algorithm verification in radiation detector readout
- Ms
Handan YILMAZ
(istanbul technical University)
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7:15 PM
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Resource-Efficient Streaming Beam Reconstruction on an Intel Max 10 FPGA
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Liqing Qin
(Heidelberg Ion Beam Therapy Centre)
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7:16 PM
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JEDI-linear: Fast and Efficient Graph Neural Networks for Jet Tagging on FPGAs
-
Zhiqiang Que
(University of Bristol)
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7:17 PM
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Reconciling Fixed-Frequency Clocking and Variable Sampling-Rate Data: Real-Time Arbitrary Resampling for Stream Processing
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Javier Galindo Guarch
(Aragon Institute of Technology Itainnova (ES))
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7:18 PM
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Low-Complexity Median Algorithm in FPGA for AMS-02 Layer-0 Upgrade
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Luca Russo
(Universita e INFN, Perugia (IT))
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7:19 PM
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AI Inference in FPGAs for both Standard and Safe & Dependable Applications
-
David Ganz
(ZHAW)
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7:20 PM
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SVN is better than GIT for FPGA development: I will die on this hill
-
Yair Linn
(TRIUMF)
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7:21 PM
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Using native libraries functions from VHDL with VHPIDIRECT
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Augusto Fraga Giachero
(CNPEM / LNLS)
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7:22 PM
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MONO: Enhancing Bit-Flip Resilience With Bit Homogeneity for Neural Networks
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Maryam Eslami
(Ruhr-Universität Bochum)
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7:23 PM
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PandA-Bambu Backend for hls4ml
-
Nicolo Ghielmetti
(CERN)
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7:24 PM
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From C/C++ to Hardware with Bambu: An Open-Source HLS Research Tool
- Mr
Tommaso Fellegara
(Politecnico di Milano)
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7:25 PM
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ARTEMIS: FPGA-based AD in the ATLAS Level-1 Trigger
-
Paula Martinez Suarez
(CERN)
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7:26 PM
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Implementation of Elias deterministic extractor for true random number generation
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Lorenzo Borella
(Universita e INFN, Padova (IT))
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7:27 PM
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The Firmware Development Kit (FDK)
-
Adam Lee Barcock
(Science and Technology Facilities Council STFC (GB))
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7:28 PM
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Frame Buffering Design Strategies for Boosting Mobipix 15D X-Ray Imaging Rates
- Mr
Allan Borgato
(LNLS)
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