Speaker
Mr
Michael Karagounis
(Bonn Physics University)
Description
A new hybrid pixel readout integrated circuit denominated FE-I4 is being developed for use in ATLAS upgrades. The design goals include 4 times higher rate capability, 4 times the active area (full reticule), and 38% smaller pixels than the presently used FE-I3 IC. The target applications are a possible smaller radius replacement of the present inner layer and/or outer layers or disks of a super-LHC detector. For the innermost layer of a super-LHC detector a further design generation will be needed, and the present effort serves as a stepping stone towards this ultimate goal. Small size analog/digital prototype blocks have been fabricated in 0.13um feature size bulk CMOS technology. An overview of the full chip design-in-progress is presented, along with status and test results from various test chip prototypes.
Primary author
Mr
Michael Karagounis
(Bonn Physics University)
Co-authors
Dr
Abderrezak Mekkaoui
(LBNL)
Dario Gnani
(LBNL)
David Arutinov
(Physikalisches Institut der Universitat Bonn)
Denis Fougeron
(CPPM Marseille)
Giovanni Darbo
(INFN Genova)
Hubertus Junker
(Physikalisches Institute der Universitat Bonn)
Jan David Schipper
(NIKHEF)
Dr
Marlon Barbero
(Physikalisches Institute der Universitat Bonn)
Maurice Garcia-Sciveres
(LBNL)
Mohsine Menouni
(CPPM Marseille)
Robert Ely
(LBNL - Lawrence Berkeley National Laboratory)
Roberto Beccherle
(INFN Genova)
Mr
Ruud kluit
(NIKHEF)
Thomasz Hemperek
(Physikalisches Institute der Universitat Bonn)
Vladimir Gromov
(NIKHEF)
