Speaker
Description
Summary
Luminosity upgrades to the LHC will mean that the ATLAS Level-1 trigger must deal with higher pileup while maintaining manageable trigger rates and high efficiency. Over the 2013-14 shutdown, firmware and hardware upgrades to the existing Level-1 Calorimeter Trigger (L1Calo) will add object coordinates and ET to the real time data path, and a new topology processor (L1Topo) will be added to Level-1. EM and hadronic tower sums are received in L1Calo by the Preprocessor, which in turn feeds two parallel processor subsystems the Jet/Energy-sum Processor (JEM) and Cluster Processor (CP). Jets and EM/hadronic clusters are identified by Jet/Energy-sum modules (JEMs) or Cluster Processor modules (CPMs), respectively. Common Merger Modules (CMMs) receive CPM/JEM results over backplane links and produce system-wide results. The upgrade to L1Calo includes upgraded CPM and JEM firmware to send trigger object data across the backplane at increased data rates. The current CMMs will be replaced by new “CMX” modules capable of receiving and processing the high-speed backplane data, and sending them over high-speed optical links to a new topological processor (L1Topo) subsystem. L1Topo will be capable of performing geometrical cuts and correlations, as well as calculate such complex observables as invariant mass. Real-time L1Topo output will be sent to the Central Trigger Processor CTP, where the final Level-1 accept decision is taken. In addition to the L1Topo architecture, we present crucial aspects of topology algorithm development, including optimal bandwidth, FPGA resources and latency.
At phase-I in 2018, the luminosity of LHC will be increased to ~ 3 × 1034cm-2s-1. To improve the ATLAS Level-1 Trigger performance at phase-I, changes are needed at both the ATLAS detector and the Level-1 Trigger system. New on-detector electronics, the digital Tower Builder Board, will be installed on the Liquid Argon Calorimeter to provide trigger higher-granularity calorimeter information. New algorithms running in additional hardware will be added to the existing Level-1 Trigger to process these data, which are expected to give the required trigger performance with higher LHC pileup of phase-I running. The new off-detector digital processing chain will consist of two subsystems: a Digital Processor System (DPS) will perform digital filtering on the new digital calorimeter data and a feature extractor subsystem with Electron and Jet processors (eFEX, jFEX) will identify calorimeter trigger signatures. The eFEX will be designed as a modular subsystem, housed in two ATCA crates and consisting of around 20 modules, each receiving data on about 200 optical fibres at 6-10 Gb/s. These input optical fibres will go through dense optical backplane connectors in the ATCA Zone-3 area and terminate on parallel embedded optical receivers near FPGAs on the main modules. Information describing objects identified by the FEX subsystems will be sent over optical fibres to a Topology Processor subsystem. We also present the motivation for architectural design choices, latest test results, and high-speed link simulations.
