Speaker
Description
Summary
The higher beam luminosity at the HL-LHC will generate higher detector data rates. The 130nm CMOS 4.8 Gbit/s gigabit transceiver (GBT) currently developed at CERN provides a radiation robust solution for the communications between LHC detectors and the control rooms.
In order to provide lower power data links, a new SerDes called low power GBT (LPGBT) will be realized with a 65 nm technology using a 1.2 V supply. The aim of this new version is to implement the same transmission protocol used in the GBT with a power reduction of a factor of four.
The two circuits presented here are designed as possible solutions for the critical serializer function in the LPGBT. Both of them use an architecture working at full data-rate and are based on a 120 bit shift register to serialize data and a “load generator” logic to load the new data in parallel to transmission. These options aim at simplifying the circuitry used in the previous version of the serializer and to reduce the power consumption.
Operation at 4.8 Gbit/s requires the use of dynamic true single phase clock flip flops (TSPC). To avoid using a regular binary counter in the load circuit, which is difficult to design at this speed, a linear feedback shift register is instead applied.
To cope with the total ionizing dose expected for this application (100 MRad/10 years), previous studies have shown that the smallest and fastest transistors available in the technology can not be used and that the minimum transistor width required is 300nm.
The first serializer ("simple-TMR") developed uses a triple module redundancy scheme to assure single event upsets (SEU) robustness through masking. Hence, three different shift registers work in parallel with voted outputs and each register has a dedicated load generator logic.
The second serializer ("code-protected") takes advantage of the Reed-Solomon code used in the GBT forward error correction (FEC) scheme. This code is designed to correct up to four corrupted 4-bit symbols per received word. The logic providing the load signals to the serializer takes advantage of this data structure to minimize the number of flip-flops that have to work at high speed while maintaining the robustness of the code. It introduces a novel way to use coding by protecting not only data from transmission errors but also the control logic.
The two serializers are included in a 3 mm x 1 mm test chip which was characterized for pre-irradiation functionality and electrical characteristics. The “simple-TMR” serializer occupies an area of 7900 µm2 and the “code-protected” serializer occupies 3900 µm2. Both of them were functionally tested at 4.8 Gbit/s showing a correct behaviour and power consumption respectively of 30 mW and 19 mW. The maximum speed achieved during tests was 5.6 Gbit/s for both serializers. A dedicate custom PCB was developed to test and characterized the chip, the test bench is completed with the use of a JBERT or GLIB card. In addition, the chip was irradiated at the Louvain-la-Neuve Heavy Ion Irradiation Facility (HIF) and the SEU robustness characteristics are also presented here.
