System-Verilog and UVM mini workshop

Europe/Zurich
13-2-005 (CERN)

13-2-005

CERN

90
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Description
Exchange of experience with use of System Verilog and UVM for design simulation and verification
Videoconference Rooms
System-Verilog_and_UVM_mini_workshop
Name
System-Verilog_and_UVM_mini_workshop
Description
Exchange of experience with use of System Verilog and UVM for design simulation and verification
Extension
109273923
Owner
Jorgen Christiansen
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    • 09:00 09:10
      Introduction 10m
      Speaker: Jorgen Christiansen (CERN)
      Slides
    • 09:10 09:30
      Development of a PCIe DMA engine verification framework 20m
      Speaker: Michal Husejko (CERN)
      Slides
    • 09:30 09:50
      Architecture optimization and design verification of the Timepix3 and the Velopix pixel ASICs 20m
      Speaker: Tuomas Sakari Poikela (University of Turku (FI))
      Slides
    • 09:50 10:10
      Design, optimization and verification of the GBT-SCA control and monitoring ASIC 20m
      Speaker: Christian Paillard (CERN)
    • 10:10 10:25
      coffee 15m
    • 10:25 10:45
      Development of a pixel ASIC verification framework 20m
      Speaker: Elia Conti (Universita e INFN (IT))
      Slides
    • 10:45 11:05
      Development of standardized CMA interface 20m
      Speaker: Marcel Alsdorf (Universitaet Bonn (DE))
      Slides
    • 11:05 11:25
      Development and verification of the TOTEM DAQ firmware 20m
      Speaker: Adrian Fiergolski (Warsaw University of Technology (PL))
      Slides
    • 11:25 11:45
      Development and verification of the ABCD130 ATLAS silicon strip ASIC 20m
      Speaker: Francis Anghinolfi (CERN)
      Slides
    • 11:45 12:05
      Verification of complex mixed signal ASICs 20m
      Speaker: Tomasz Hemperek (Universitaet Bonn (DE))
      Slides
    • 12:05 12:25
      Discussion 20m