System-Verilog and UVM mini workshop

Thursday 14 Nov 2013, 09:00 → 13:00 Europe/Zurich

13/2-005 (CERN)

Exchange of experience with use of System Verilog and UVM for design simulation and verification

09:00 → 09:10 Introduction

Speaker: Jorgen Christiansen (CERN)

Slides SV_UVM_miniworkshop.pdf SV_UVM_miniworkshop.pptx

09:10 → 09:30 Development of a PCIe DMA engine verification framework

Speaker: Michal Husejko (CERN)

Slides Development_of_a_PCIe_DMA_engine_verification_framework.pdf

09:30 → 09:50 Architecture optimization and design verification of the Timepix3 and the Velopix pixel ASICs

Speaker: Tuomas Sakari Poikela (University of Turku (FI))

Slides SV_UVM_workshop_Tuomas_Poikela_14_11_2013.pdf SV_UVM_workshop_Tuomas_Poikela_14_11_2013.pptx

09:50 → 10:10 Design, optimization and verification of the GBT-SCA control and monitoring ASIC

Speaker: Christian Paillard (CERN)

10:10 → 10:25 coffee

10:25 → 10:45 Development of a pixel ASIC verification framework

Speaker: Elia Conti (Universita e INFN (IT))

Slides VE_pixel_chip_model-v1.2.pdf VE_pixel_chip_model-v1.2.pptx

10:45 → 11:05 Development of standardized CMA interface

Speaker: Marcel Alsdorf (Universitaet Bonn (DE))

Slides UVM_for_CMA.pdf

11:05 → 11:25 Development and verification of the TOTEM DAQ firmware

Speaker: Adrian Fiergolski (Warsaw University of Technology (PL))

Slides presentation.pdf

11:25 → 11:45 Development and verification of the ABCD130 ATLAS silicon strip ASIC

Speaker: Francis Anghinolfi (CERN)

Slides UVM_for_ABC.pdf UVM_for_ABC.pptx

11:45 → 12:05 Verification of complex mixed signal ASICs

Speaker: Tomasz Hemperek (Universitaet Bonn (DE))

Slides Verification_of_complex_mixed_signal_ASICs_-_CERN_-_12_November_2013.pdf Verification_of_complex_mixed_signal_ASICs_-_CERN_-_12_November_2013.pptx

12:05 → 12:25 Discussion