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Please use CTRL + C to copy this URLDetailed timetable
System-Verilog and UVM mini workshop
Thursday, 14 November 2013 from to (Europe/Zurich)
at CERN ( 13-2-005 )
at CERN ( 13-2-005 )
Exchange of experience with use of System Verilog and UVM for design simulation and verification
Vidyo public room : System-Verilog_and_UVM_mini_workshop More Info | Join Now!
Go to day
Speaker: Jorgen Christiansen (CERN) Material: Slides
Development of a PCIe DMA engine verification framework
Speaker: Michal Husejko (CERN) Material: Slides
Architecture optimization and design verification of the Timepix3 and the Velopix pixel ASICs
Speaker: Tuomas Sakari Poikela (University of Turku (FI)) Material: Slides
Design, optimization and verification of the GBT-SCA control and monitoring ASIC
Speaker: Christian Paillard (CERN)
- 10:10 - 10:25 coffee
Development of a pixel ASIC verification framework
Speaker: Elia Conti (Universita e INFN (IT)) Material: Slides
Development of standardized CMA interface
Speaker: Marcel Alsdorf (Universitaet Bonn (DE)) Material: Slides
Development and verification of the TOTEM DAQ firmware
Speaker: Adrian Fiergolski (Warsaw University of Technology (PL)) Material: Slides
Development and verification of the ABCD130 ATLAS silicon strip ASIC
Speaker: Francis Anghinolfi (CERN) Material: Slides
Verification of complex mixed signal ASICs
Speaker: Tomasz Hemperek (Universitaet Bonn (DE)) Material: Slides
- 09:00 - 09:10 Introduction 10'