System-Verilog and UVM mini workshop

Thursday, 14 November 2013 from to (Europe/Zurich)
at CERN ( 13-2-005 )
Description
Exchange of experience with use of System Verilog and UVM for design simulation and verification
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  • Thursday, 14 November 2013
    • 09:00 - 09:10 Introduction 10'
      Speaker: Jorgen Christiansen (CERN)
      Material: Slides powerpoint file pdf file
    • 09:10 - 09:30 Development of a PCIe DMA engine verification framework 20'
      Speaker: Michal Husejko (CERN)
      Material: Slides pdf file
    • 09:30 - 09:50 Architecture optimization and design verification of the Timepix3 and the Velopix pixel ASICs 20'
      Speaker: Tuomas Sakari Poikela (University of Turku (FI))
      Material: Slides powerpoint file pdf file
    • 09:50 - 10:10 Design, optimization and verification of the GBT-SCA control and monitoring ASIC 20'
      Speaker: Christian Paillard (CERN)
    • 10:10 - 10:25 coffee
    • 10:25 - 10:45 Development of a pixel ASIC verification framework 20'
      Speaker: Elia Conti (Universita e INFN (IT))
      Material: Slides powerpoint file pdf file
    • 10:45 - 11:05 Development of standardized CMA interface 20'
      Speaker: Marcel Alsdorf (Universitaet Bonn (DE))
      Material: Slides pdf file
    • 11:05 - 11:25 Development and verification of the TOTEM DAQ firmware 20'
      Speaker: Adrian Fiergolski (Warsaw University of Technology (PL))
      Material: Slides pdf file
    • 11:25 - 11:45 Development and verification of the ABCD130 ATLAS silicon strip ASIC 20'
      Speaker: Francis Anghinolfi (CERN)
      Material: Slides powerpoint file pdf file
    • 11:45 - 12:05 Verification of complex mixed signal ASICs 20'
      Speaker: Tomasz Hemperek (Universitaet Bonn (DE))
      Material: Slides powerpoint file pdf file
    • 12:05 - 12:25 Discussion 20'