Conveners
ASICs: A1a
- Christophe De La Taille (OMEGA (FR))
ASICs: A1b
- Christophe De La Taille (OMEGA (FR))
ASICs: A2
- Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))
ASICs: A3a
- Alessandro Marchioro (CERN)
ASICs: A3b
- Alessandro Marchioro (CERN)
ASICs: A4
- Christophe De La Taille (OMEGA (FR))
ASICs: A5a
- Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))
ASICs: A5b
- Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))
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Matthew Noy (CERN)23/09/2014, 09:50ASICsOralThe TDCPix is a hybrid pixel detector readout ASIC designed for the NA62 GigaTracker detector. The asynchronously operating pixel array consists of 1800 pixels, each 300x300$\mu m^2$. The requirements are a single-hit timing resolution better than 200ps RMS and read-out efficiency of 99% or better. The time-walk effect is compensated by in-pixel time-over-threshold discriminators...Go to contribution page
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Giovanni Mazza (INFN sez. di Torino)23/09/2014, 10:15ASICsOralToPiX v4 is the prototype for the readout of the silicon pixel sensors of the Micro Vertex Detector for the PANDA experiment. ToPiX provides position, time and energy measurement of the incoming particles and is designed for the trigger-less environment foreseen in PANDA. The prototype includes 640 pixels with a size of 100x100 um2, a 160 MHz time stamp distribution circuit to measure...Go to contribution page
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Dr Frederic MOREL (IPHC-IN2P3, UDS)23/09/2014, 11:10ASICsOralTwo CMOS Pixel Sensors (CPS) flavours: MISTRAL and ASTRAL, dedicated to the upgrade of the Inner Tracking System (ITS) of the ALICE experiment are being designed at IPHC in Strasbourg. Each of two sensors is composed of three identical units called FSBB (Full Scale Building Block), multiplexed towards the external word. This paper will show the design and the laboratory test results of FSBB-M...Go to contribution page
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Toshinobu Miyoshi (KEK)23/09/2014, 11:35ASICsOralSOI monolithic pixel sensor has been developed using 0.2 um SOI pixel process technology. Pixel diodes are formed on SOI substrate and then pixel front end electronics are formed in 40nm thin SOI layer. Tungsten vias are used to connect the diode and electronics. A simple source follower circuit, charge sensitive preamplifier, comparator, and counter are designed in a pixel area. The minimum...Go to contribution page
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Theresa Obermann (Universitaet Bonn (DE))23/09/2014, 14:50ASICsOralNew monolithic pixel detector concepts, which integrate the front-end circuitry and the sensor on the same silicon substrate, are being explored for track reconstruction in future particle physics experiments. The innovative concept of Depleted Monolithic Active Pixel Sensors (DMAPS) is based on a high resistive silicon bulk material enabling full substrate depletion with creation of an...Go to contribution page
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Francis Anghinolfi (CERN)23/09/2014, 15:15ASICsOralThe ABC130 Front End ASIC for the ATLAS Silicon Strip upgrade has been designed and fabricated in IBM 130nm CMOS technology. It uses a binary architecture with fixed trigger latency, similar to that used in the current experiment, but the functionality is extended to support two readout mechanisms: one with low latency to support region of interest track trigger construction, and the other for...Go to contribution page
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Marek Idzik (AGH University of Science and Technology (PL))23/09/2014, 15:40ASICsOralSilicon strip detectors in the upgraded Tracker of LHCb experiment will require a new readout ASIC. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. The ASIC front-end comprises a charge preamplifier and a shaper. Fast shaping is required ($T_{peak}=25ns$, fast recovery) to distinguish between the LHC bunch crossings....Go to contribution page
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David Gascon (ICC-UB)24/09/2014, 09:50ASICsOralThe design of a 128 channel ASIC (PACIFIC) for the upgrade of LHCb tracker system is presented. The detector will be made of scintillating fibers and read out by 128 channel SiPM arrays. PACIFIC chip will be connected to a SiPM without any external component. It includes analog signal processing and digitization. The first stage is a current conveyor followed by a tunable fast shaper (~10ns)...Go to contribution page
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Paolo Carniti (Universita & INFN, Milano-Bicocca (IT))24/09/2014, 10:15ASICsOralThe CLARO-CMOS is a prototype ASIC for fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of about 1 mW per channel. The chip was designed in 0.35 micron CMOS technology, and was tested for radiation tolerance with neutrons up to 10$^{14}$ 1 MeV neq/cm$^2$ and protons and X-rays up to 8 Mrad. Its capability to readout single...Go to contribution page
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Ludovic Raux (OMEGA Ecole Polytechnique -CNT)24/09/2014, 11:10ASICsOralThe SPIROC and TRIROC chips are complete dedicated very front-end electronics for the readout of SiPM. Designed with AMS 0.35 µm SiGe technology, they enable to digitize and process signal over such a large dynamic range ADC. SPIROC has been extensively used for calorimeters by different groups for ILC (International Linear Collider) HCAL and ECAL prototypes. With its 64-channel readout,...Go to contribution page
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Eduardo Picatoste Olloqui (University of Barcelona (ES))24/09/2014, 11:35ASICsOralAn integrated circuit for the Upgrade of the LHCb Calorimeter front end electronics is presented. It includes four analog channels, a Delay Locked Loop (DLL) for signal phase synchronization for all channels and an SPI communication protocol based interface. The analog circuit is based on two fully differential interleaved channels with a switched integrator to avoid dead time and includes...Go to contribution page
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Jakub Moron (AGH University of Science and Technology (PL))24/09/2014, 14:00ASICsOralThe design and preliminary measurement results of a multichannel, variable gain front-end electronics for LumiCal detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier and CR-RC shaper with pole-zero cancellation circuit. Measurement results confirm full...Go to contribution page
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Prof. Yun Chiu (The University of Texas at Dallas)24/09/2014, 14:25ASICsOralWe present the design of a 12-bit, 160-MSPS two-step SAR ADC in 40-nm CMOS with calibration and radiation test results. The ADC measured 67.5-dB SNDR and ≥85-dB SFDR that displayed minimal degradation after being exposed to a total ionizing dose of up to 1 Mrad. The power consumption is 4.5 and 6.1 mW at 80 and 160 MSPS, respectively. The small die size also opens up good potential for single...Go to contribution page
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Gianluigi De Geronimo (Brookhaven National Laboratory (US))24/09/2014, 14:50ASICsOralWe present VMM2, an ASIC for charge-interpolating trackers designed for use with Micromegas and sTGC in the ATLAS Muon upgrade. It integrates 64 channels, each providing charge amplification, discrimination, neighbor logic, amplitude and timing measurements, analog-to-digital conversions, and either direct or multiplexed readout. The front-end amplifier can operate with a wide range of input...Go to contribution page
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Mr Jeffrey Prinzie (KU Leuven)24/09/2014, 15:15ASICsOralA radiation hardened Time-to-Digital Converter (TDC) has been designed with < 10 ps single-shot resolution using resistive interpolation. The TDC uses a DLL based control loop to calibrate gate delays to a reference clock. The control loop uses a novel low bandwidth Bang-Bang phase detector in combination with a high bandwidth dead-zone PFD for fast recovery after single-event strikes. The...Go to contribution page
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Gianluca Traversi (Universita e INFN (IT))24/09/2014, 15:40ASICsOralThis work is concerned with the design and characterization of bandgap reference circuits capable of operating with a power supply of 1.2V in view of applications to HL-LHC experiments. Due to the harsh environment foreseen for these devices, different solutions have been considered and implemented in a 65nm CMOS technology. Together with a conventional structure which exploits bipolar...Go to contribution page
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Federico Faccio (CERN)25/09/2014, 09:49ASICsOralA 10W converter ASIC, called FEAST2, has been developed for LHC experiment upgrades. It has been proved to be tolerant up to more than 500Mrad(Si) TID and an integrated particle fluence of 5x1014n/cm2. FEAST2 has been also tested for SEE up to a LET=64MeVcm2mg-1 without output power interruptions. FEAST2 is embedded in two modules called FEASTMP and FEASTMN (with positive and negative output...Go to contribution page
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Mr Vladimir Gromov (Nikhef)25/09/2014, 10:14ASICsOralWe report on a prototype of a 5.12 Gbps Data Serializer and Wireline Transmitter circuit in 130 nm CMOS technology. A shift-register-free topology has been used in the serializer block. A 16-to-1 multiplexer selects one bit of data at a time from either a posedge triggered section or a negedge triggered section of a 16-bit input register clocked at 320 MHz. The serializer consumes only 15 mW...Go to contribution page
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Ms Xiaoting Li (Central China Normal University, Southern Methodist University)25/09/2014, 11:10ASICsOralWe present the designs and testing results of a single-channel and a two-channel VCSEL driver and a four-channel array VCSEL driver ASICs for the LHC detector upgrade. All ASICs are fabricated in a commercial 0.25-µm Silicon-on-Sapphire CMOS technology. LOCld1 and LOCld2 are designed to drive differentially VCSEL TOSAs, whereas LOCld4 is designed to drive a VCSEL array die. LOCld1/LOCld2 and...Go to contribution page
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Ping Gui (SMU)25/09/2014, 11:35ASICsOralThe GigaBit Laser Driver (GBLD) is a key on-detector component of the GigaBit Transceiver (GBT) system on the transmitter side. As part of design efforts towards the upgrade of electrical components for the future LHC experiments, a 10 Gb/s GBLD (GBLD10) was developed in 130 nm CMOS technology. The GBLD10 is based on the distributed-amplifier architecture with pre-emphasis to achieve data...Go to contribution page