Speakers
Dario Bisello
(Universita e INFN (IT))Dr
LILI DING
(INFN, Padova; Department of Information Engineering, Padova University, Italy)Dr
Marta BAGATIN
(Department of Information Engineering, Padova University, Italy)
Description
Abstract: The paper reports the 65 nm CMOS transistors exposed to 3 MeV proton to study the total ionizing dose (TID) effect and displacement damage (DD) together. The proton fluence of 7×1014 p/cm2 is equivalent with 1 Grad(SiO2) total dose and 1016 n/cm2 1 MeV neutron. Under this unprecedented hostile environment, the degradation of 65 nm CMOS transistors was mainly due to TID effect. Referring to the results from 10-keV X-ray irradiation, no visible DD-induced degradation could be observed even for this extremely high proton fluence.
Keyword: 3 MeV proton; total ionizing dose effect; displacement damage; 65 nm CMOS
I. Introduction:
Investigation of radiation damage in harsh environment continues to be essential, since the increasing radiation dose and particle fluence to which semiconductor detectors are intended to be exposed. In the High Energy Physics (HEP) field, there are not only low energy electrons and photons, but also protons, neutrons and other particles which own the ability to induce displacement damage. To evaluate the radiation damage under the mixed environment, 3 MeV proton can be a good candidate as the radiation source. With the fluence of 7×1014 p/cm2, combining with the LET in SiO2 of 9.3×10-2 MeV.cm2/mg and the NIEL in Si of 5.2×10-5 MeV.cm2/mg, the deposited dose is calculated to be 1 Grad(SiO2), whereas the 1 MeV neutron equivalent fluence is about 1016 n/cm2. Thus, this radiation source can be used to evaluate the radiation damage under hostile radiation environment.
II. Irradiation setup:
The irradiation was performed in room temperature and in vacuum chamber. The proton beam was produced by the CN accelerator at INFN Laboratori Nazionali di Legnaro (Padova), with the kinetic energy of 3 MeV and a maximum proton current of 1 μA.
Before irradiation, the beam uniformity was checked by a Gafchromic radiology film which was exposed to the beam for few seconds. Then the beam was carefully aligned to make sure that the sample could be placed in the region of uniform beam. The beam intensity was measured with a Faraday cup before and after each exposure. During irradiation, the relative fluence was continuously monitored and adjusted by the current on the sample.
The irradiated samples were designed by CERN, fabricated by TSMC, wire-bonded and tested in Padova. The samples were CMOS transistors in a commercially available 65 nm CMOS technology, with 1.8 nm gate oxide and 1.2 V supply voltage.
The irradiation was performed at a flux of 4×1010 p/cm2/s for the first region when the fluence is lower than 7×1013 p/cm2, then 4×1011 p/cm2/s when the fluence is between 7×1013 p/cm2 and 7×1014 p/cm2. During irradiation and the following annealing, the transistors were kept under “worst case” bias: for nMOS, the gate was kept at 1.2 V whereas all other terminals grounded; for pMOS, all the terminals were grounded.
III. Results and discussion:
From the results in Fig. 1., along with the increase of the proton fluence, the evolution of Vth shift is consistent with the radiation damage due to the total ionizing dose (TID) effect. For nMOS transistors, the competition between the positive trapped charge and the negative interface traps could be observed. Considering the thin gate oxide (1.8 nm), the trapped charge and interface traps should be mainly built up in the STI oxide. This is proved by the radiation-induced narrow channel (RINC) effect, where the narrowest transistor (120/60 nm) performing the biggest negative shift. After annealing, due to the progressive accumulation of interface traps, for most of the transistors, Vth keeps increasing. For pMOS transistors, due to the buildup of the positive trapped charge and the positive interface traps during irradiation, the absolute value of Vth keeps increasing. Meanwhile, although the Vth shift of transistors with geometries from 240/60 nm to 1 μm/60 nm almost overlap, it still could be observed that the biggest shift is according to the narrowest transistor (120/60 nm).
Fig. 1. Evolution of the shift of Vth along with the increase of the proton fluence for 65-nm nMOS (a) and pMOS transistors (b), when the proton fluence arrives at 7×1014 p/cm2, the deposited dose is of 1 Grad(SiO2) and the 1 MeV neutron equivalent fluence is about 1016 n/cm2.
From the historical point of view, CMOS transistors are not very sensitive to displacement damage (DD) due to its nature as a “majority carrier device”. However, since this is an unprecedented hostile environment, it is necessary to evaluate the comparative sensitivity of CMOS transistors to DD.
If only from Fig. 1., it is difficult to evaluate the degradation level of the transistors due to DD independently. Referring to the structure of the samples, there are ESD protection diodes connected with the gate contact of every transistor. Therefore, the evolution of the gate leakage can be used as an indicator of DD in diodes. In addition, 10-keV X-ray irradiation was performed for comparison due to the negligible NIEL of the photon. The ratio variations of gate leakage and on-state drain current of 360/60 nm nMOS transistors together with the accumulation of X-ray dose or the increase in proton fluence are presented in Fig. 2. Under the X-ray environment, the increase of gate leakage was negligible, whereas this increase was quite big under the 3-MeV proton environment, suggesting the evident damage related with DD. However, under both the two environments, the on-state currents of the nMOS transistors did not behave big difference, considering that there are also the differences in radiation source and dose rate, no visible DD-induced degradation could be observed even for this extremely high proton fluence (7×1014 p/cm2 ,with the 1 MeV neutron equivalent fluence of 1016 n/cm2).
Fig. 2. Ratio variation of gate leakage IG (with VG=1.2 V) (a) and drain current (with VG=VD=1.2 V) (b) of 360/60 nm nMOS transistors under 3-MeV proton and 10-keV X-ray irradiation environment.
IV. Conclusion:
TID effect and DD in 65 nm CMOS transistors were investigated together by 3 MeV proton. The fluence of proton beam was up to 7×1014 p/cm2, which was equivalent with 1 Grad(SiO2) total dose and 1016 n/cm2 1 MeV neutron. Therefore, 3 MeV proton is a good candidate to evaluate the radiation damage under the mixed environment. Under this unprecedented hostile environment, the 65 nm CMOS transistors behaved visible degradation which was consistent with the TID-induced degradation. To study the DD-induced degradation, 10-keV X ray irradiation was performed for comparison, the results suggests that no visible DD could be observed even for this extremely high proton fluence.
Summary
TID effect and DD in 65 nm CMOS transistors were investigated together by 3 MeV proton. The fluence of proton beam was up to 7×1014 p/cm2, which was equivalent with 1 Grad(SiO2) total dose and 1016 n/cm2 1 MeV neutron. Therefore, 3 MeV proton is a good candidate to evaluate the radiation damage under the mixed environment. Under this unprecedented hostile environment, the 65 nm CMOS transistors behaved visible degradation which was consistent with the TID-induced degradation. To study the DD-induced degradation, 10-keV X ray irradiation was performed for comparison, the results suggests that no visible DD could be observed even for this extremely high proton fluence.
Primary author
Dr
LILI DING
(INFN, Padova; Department of Information Engineering, Padova University, Italy)
Co-authors
Alessandro Paccagnella
(U)
Dario Bisello
(Universita e INFN (IT))
Dr
Marta BAGATIN
(Department of Information Engineering, Padova University, Italy)
Dr
Serena Mattiazzo
(Department of Physics and Astronomy, Padova University, Italy)
Mr
Simone Gerardin
(Padova University)
