Sep 2 – 9, 2007
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FPGA based Compute Notes for High Level Triggering in PANDA

Sep 3, 2007, 8:00 AM
10h 10m
Victoria, Canada

Victoria, Canada

Board: 3
poster Online Computing Poster 1


Prof. Wolfgang Kuehn (Univ. Giessen, II. Physikalisches Institut)


PANDA is a new universal detector for antiproton physics at the HESR facility at FAIR/GSI. The PANDA data acquisition system has to handle interaction rates of the order of 10**7 /s and data rates of several 100 Gb /s. FPGA based compute nodes with multi-Gb/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Data connectivity is provided via optical links as well as multiple Gbit Ethernet ports. The boards will support trigger algorithms such us pattern recognition for RICH detectors, EM shower analysis, fast tracking algorithms and global event characterization. A high level hardware description language (Handel-C) will be used to implement the firmware.
Submitted on behalf of Collaboration (ex, BaBar, ATLAS) PANDA

Primary author

Prof. Wolfgang Kuehn (Univ. Giessen, II. Physikalisches Institut)

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