Sep 2 – 9, 2007
Victoria, Canada
Europe/Zurich timezone
Please book accomodation as soon as possible.

Addressing Future HPC Demand with Multi-core Processors

Sep 5, 2007, 11:30 AM
Carson Hall (Victoria, Canada)

Carson Hall

Victoria, Canada


S. Pawlowski (Intel)


Dozens of cores will not be a dream. Multiple processor cores drive energy efficient performance for highly parallel applications. However, looking beyond cores, achieving balanced high performance throughput has many challenges. Intel Senior Fellow and CTO of Digital Enterprise Group Steve Pawlowski will provide his technology vision to address bandwidth, capacity and power needs on memory, I/O, intra-chip and inter-chip interconnections and outlook on future reliability challenges.


Stephen S. Pawlowski is an Intel Senior Fellow. He is the Digital Enterprise Group chief
technology officer and general manager for Architecture and Planning for Intel

Pawlowski joined Intel in 1982. He led the design of the first Multibus I Single Board
Computer based on the 386 processor. He was a lead architect and designer for Intel's
early desktop PC and high performance server products and was the co-architect for
Intel's first P6 based server chipsets. He helped define the system bus interfaces for
Intel's P6 family processors, the Pentium® 4 processor and Itanium™ processor. He
also created and led the research for Intel's agile radio architecture for a future
generation of wireless products and prior to his current assignment was the director of
Corporate Technology Group's Microprocessor Technology Lab.

Pawlowski graduated from the Oregon Institute of Technology in 1982 with bachelor's
degrees in electrical engineering technology and computer systems engineering
technology, and received a master's degree in computer science and engineering from
the Oregon Graduate Institute in 1993.

Pawlowski holds 56 patents in the area of system, and microprocessor technologies.
He has received three Intel Achievement Awards.

Presentation materials