Jun 5 – 10, 2016
Padova, Italy
Europe/Rome timezone

An I/O Controller for Real Time Distributed Tasks in Particle Accelerators

Jun 7, 2016, 3:00 PM
1h 30m
Centro Congressi (Padova)

Centro Congressi


Poster presentation Real Time System Architectures and Intelligent Signal Processing Poster session 1


Dr Davide Pedretti (Universita e INFN, Legnaro (IT)) Dr Stefano Pavinato (INFN - National Institute for Nuclear Physics)


SPES is a second generation ISOL radioactive ion beam facility in construction at the INFN National Laboratories of Legnaro (LNL). Its distributed control system embeds custom control in almost all instruments or cluster of homogeneous devices. Nevertheless, standardization is an important issue that concerns modularity and long term maintainability for a facility that has a life span of at least twenty years. In this context, the research project presented in this paper focuses on the design of a custom IOC (Input Output Controller) which acts as a local intelligent node in the distributed control network and is generic enough to perform several different tasks spanning from security and surveillance operations, beam diagnostic, data acquisition and data logging, real time processing and trigger generation. The IOC exploits the COM (Computer On Module) Express standard that is available in different form factors and processors, fulfilling the computational power requirement of varied applications. The Intel x86-64 architecture makes software development straightforward, easing the portability. The result is a custom motherboard with several application specific features and generic PC functionalities. The design is modular to a certain extent, thanks to an hardware abstraction layer and allows the development of soft and hard real time applications by means of a real time Operating System and of an on-board FPGA closely coupled to the CPU. Three PCIe slots, a FPGA Mezzanine Card (FMC) connector and several general-purpose digital/analog inputs/outputs enable functionality extensions. An optical fiber link connected to the FPGA is an high speed interface for high throughput data acquisitions or timing sensitive applications. The power distribution complies the AT standard and the whole board can be supplied via Power Over Ethernet (POE+) IEEE 802.3at standard. Networking and device-to-cloud connectivity are guaranteed via a gigabit ethernet link. The design, performance of the prototypes and intended usage will be presented.

Primary authors

Dr Davide Pedretti (Universita e INFN, Legnaro (IT)) Dr Stefano Pavinato (INFN - National Institute for Nuclear Physics)


Dr Damiano Bortolato (Universita e INFN, Padova (IT)) Mr Davide Marcato (INFN - LNL) Mr Fabio Gelain (INFN - LNL) Dr Marco Angelo Bellato (Universita e INFN, Padova (IT)) Dr Marco Betti (INFN-LNL) Mr Roberto Isocrate (Universita e INFN, Padova (IT))

Presentation materials