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Description
This paper presents the SAMPA, a new ASIC for the ALICE upgrade for Time Projection chamber (TPC) and Muon chamber (MCH) read-out frontend electronics.
The SAMPA ASIC is designed in 130nm CMOS technology with 1.2V nominal power supply. SAMPA includes 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel comprises a Charge Sensitive Amplifier, a shaping stage, and a 10-bit ADC. A DSP block and 11 SLVS output links (throughput up to 3.2 Gbps) complete the chip.
Experimental results of the first complete ASIC prototype will be presented.
Summary
Operating the ALICE TPC (Time Projection Chamber) at a Pb-Pb collision rate of 50 kHz requires to replace the present MWPC based read-out by GEM detectors, which feature intrinsic ion blocking without additional gating and exhibit excellent rate capabilities. As the drift time is higher than the average time between interactions, a trigger-less continuous read-out is required, which is not supported by the present front-end electronics. Also in the case of the Alice Muon Chambers (MCH) detector, the present front-end electronics installation does not cope with the future (higher interaction rate) running conditions and needs to be replaced. Thus, the new read-out ASIC, named SAMPA, is developed to serve both the TPC and Muon Chamber read out.
The SAMPA ASIC integrates 32 channels of the full data processing chain, it is designed in TSMC 130 nm CMOS technology with nominal voltage supply of 1.2 V and it supports continuous and triggered read-out. The SAMPA consumes an area of about 86 mm$^2$
It comprises positive/negative polarity Charge Sensitive Amplifiers (CSA), which transform the charge signal into a differential semi-Gaussian voltage signal, which is then digitized by a 10-bit 10 Msamples/s ADC. After the ADC, a digital signal processor allows baseline shifts correction and zero suppression; unprocessed direct throughput of the full data stream is also possible. The data read-out takes place, either continuously or in triggered mode, by enabling up to eleven 320 Mbps SLVS serial links, allowing a data throughput of up to 3.2 Gbps.
The CSA shaping time can be configured to operate at 160 ns, with sensitivity of 20 mV/fC or 30 mV/fC (TPC case), or at 300 ns, with a sensitivity of 4 mV/fC (MCH case).
Second SAMPA submission included the fist complete designed ASIC chip and a set of mini-chips containing the different functional sub-blocks (analog stage, ADC, SLVS drivers, etc.).
Results of the tests performed on both the functional blocks and on prototypes from the first complete ASIC will be presented, and compared with the simulation results. The chip performance and specifications will be fully discussed.
