Speaker
Description
The ALICE Collaboration is preparing a major detector upgrade for the LHC Run 3, which includes the construction of a new silicon pixel based Inner Tracking System (ITS). The ITS readout system consists of 192 readout boards to control the sensors and their power system, receive triggers, and deliver sensor data to DAQ. To prototype various aspects of this readout system of the ITS, an FPGA based carrier board and an associated daughter card containing the CERN Gigabit Transceiver (GBT) chipset has been developed. This contribution describes laboratory and radiation testing results with this prototype board set.
Summary
The ALICE experiment is studying strongly interacting hadronic matter using nucleus-nucleus, proton-nucleus, and proton-proton collisions at the CERN LHC. To deal with the increased interaction rates expected for Run-3, the ALICE detector will be upgraded during the LHC shutdown 2019/20. The upgrades include a new, high-resolution, low-material Inner-Tracking System (ITS) based on Monolithic Active Pixel Sensors (MAPS) developed by the ITS collaboration. A total of 25k sensors are distributed in 7 concentric barrels (radii 22 - 400mm), sub-divided into staves (29 – 150cm length) and provide a detection area of 10m2 segmented into more than 12.5 G Pixels. On the inner 3 barrels, each stave consists of 9 sensors with individual data lines, while in the outer 4 barrels, sensors are combined into “modules” consisting of 2 rows of 7 sensors, where 1 “master” sensor collects the data from 6 “slave” sensors and sends them over 1 data line. These modules are arranged into 2 rows of 4 (7) modules for the middle (outer) 2 barrels.
The ITS upgrade requires a new readout system designed to be able to read the ITS data up to a rate of 100kHz (400kHz) for Pb-Pb (pp) collisions. The readout system connects to the sensor data, control, and clock lines on the detector side, receives trigger and control information from the control room, and delivers sensor data to the data acquisition system over (bi-directional) optical fibers to the control room. The readout system also needs to fulfill ancillary functions like controlling and monitoring the power system in order to quickly detect and interrupt latch-up states in the sensors.
The current readout unit design foresees a modular Readout Unit (RU), each connected to one stave, resulting in a total of 192 RU’s for ITS. The RU’s will be located 5m from the end of the staves in the experimental hall. This location is characterized by a radiation environment resulting in a total ionizing dose < 10krad and a high-energy hadron flux (capable of causing electronics single-event upsets) of ~1kHz*cm^{-2}. The RU’s thus need to be designed radiation tolerant while being able to deal with the high-speed data links of the sensors. The design consists of an FPGA to handle the data collection and formatting, as well as the control of the sensors, and a radiation-hard fiber-optic transmission chipset, the “Gigabit Transceiver Optical Link” (GBT) developed at CERN for the LHC experiment upgrades. The GBT consists of the GBTx serializer/deserializer ASIC, the VTRx/VTTx optical transceiver/transmitter module, and the GBT-SCA slow controls ASIC.
In order to evaluate various aspects of this design including the radiation tolerance, a prototype RU has been designed based on a Kintex-7 FPGA carrier board and a mezzanine that accommodates the GBT chipset. This contribution will describe the GBT associated hardware and firmware design as well as bench and radiation tests performed with these prototypes.
