Sep 25 – 29, 2006
Valencia, Spain
Europe/Zurich timezone

Local Trigger Processor Interface Module

Sep 27, 2006, 4:20 PM
1h 40m
Valencia, Spain

Valencia, Spain

IFIC – Instituto de Fisica Corpuscular Edificio Institutos de Investgación Apartado de Correos 22085 E-46071 València SPAIN


Diogo Nunes Caracinha (Faculdade de Ciencias)


The interface between the ATLAS Central Trigger Processor (CTP) and the sub- detectors read-out systems is done through the Local Trigger Processor modules. These modules allow each sub-system to either run in global mode when it gets the timing and trigger signals from the CTP or in local mode when it handles locally its trigger and timing signals. During the commissioning phase of the detector and for test purposes, it may be necessary to have several sub-detectors able to run locally with the same timing and trigger signals (e.g the calorimeters and the level-1 calorimeter). Although feasible with the current LTP modules, an extra interface module (LTPIM) has been designed in order to void the need for adhoc cabling. The LTPIM is a 6U VME64x module housing two Altera Cyclone FPGAs for VME interfacing and control. All inputs and outputs are configurable through VME accesses. Special care has been taken for handling possible long distance LVDS transmission using active equalizers. The timing of all signals can be adjusted by means of individually programmable delay circuits. The delay circuits, as well as the active equalizers, use an I2C comunication bus controlled by the control FPGA. A description of the module as well as test results will be presented.

Primary authors

Diogo Nunes Caracinha (Faculdade de Ciencias) Dr Philippe Farthouat (CERN)


Prof. Antonio Amorim (Faculdade de Ciencias) Prof. Guiomar Evans (Faculdade de Ciencias) Prof. Jose Soares Augusto (Faculdade de Ciencias) Mr Per Gällnö (CERN)

Presentation materials