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Description
Summary
The ALICE Detector Data Link (DDL) is a high-speed, duplex, point-to-point optical
link designed to interface the readout electronics of all the ALICE sub-detectors
to the DAQ computers in a standard way. The DDL consists of the Source Interface
Unit (SIU), an optical cable of up to 300 meters, and the Destination Interface
Unit (DIU). The DDL provides enough bandwidth to transfer data from the detectors
at 200 MB/s. The SIU will be attached to the Front-end Electronics; hence it will
be exposed to the radiation caused by the interacting particles. According to the
latest simulations, the highest radiation level for the SIU card is expected at the
inner radius of the TPC detector, where the total ionizing dose is 1.3 krad and the
1 MeV equivalent neutron fluence is 1.47 × 1011 neutrons/cm2 for 10 years of
operation.
In the previous, prototype versions of the DDL SIU cards the logic functions of the
DDL protocol was implemented in SRAM-based FPGA devices. According to several
radiation tolerance measurements, beside single bit errors caused in the registers
and in the embedded memory cells of the device, the high-energy particles may also
alter the content of the configuration memory cells of the device causing the
corruption or loss of the device configuration. Therefore we changed from SRAM
based FPGA to another type of logic devices, namely to an ACTEL ProASIC3 FPGA. This
device is based on flash memory technology that is inherently much more insensitive
to configuration loss. The first irradiation measurements carried out on the new
SIU card proved that no device configuration loss occurred and the number of errors
in the FPGA register cells due to the radiation also remained negligible compared
to the bit-error rate always present during optical transmission. However, the
number of bit errors in the embedded memory cells of the FPGA used for data
buffering was too high to be left undetected. In order to detect these bit errors
that may occur in these memory cells, we also implemented parity check logic in the
FPGA device.
In order to test and verify this redesigned, radiation tolerant SIU card we
developed and carried out several series of radiation tolerance tests and
measurements. With these tests we measured the register and memory bit error rates
and tested they detection in radiation environment. The series of measurements were
carried out at TSL, (Uppsala, Sweden) using protons at energy of 150 MeV and 180
MeV and at ATOMKI (Debrecen, Hungary) using neutrons with spectrum extending up to
En=14 MeV. The methods and the results of the measurements are shown in this paper.
