Sep 25 – 29, 2006
Valencia, Spain
Europe/Zurich timezone

The Front End Electronics of the Scintillator Pad Detector of LHCb Calorimeter

Sep 26, 2006, 12:10 PM
25m
Valencia, Spain

Valencia, Spain

IFIC – Instituto de Fisica Corpuscular Edificio Institutos de Investgación Apartado de Correos 22085 E-46071 València SPAIN

Speaker

David Gascon (D. ECM, Universitat de Barcelona)

Description

In this paper the Front End electronics of the Scintillator Pad Detector (SPD) is outlined. The SPD is a sub-system of the Calorimeter of the LHCb experiment designed to discriminate between charged particles and neutrals for the first level trigger. The complete system design is presented, describing its different functionalities implemented through three different cards and two ASICs. These functionalities are signal processing and digitization, data transmission, interface with control and timing systems of the experiment, low voltage power supply distribution and monitoring. Special emphasis is placed on installation and commissioning subjects such cabling, grounding, shielding and power distribution.

Summary

In this paper we will present a system level design view of the Front End electronics
of SPD. The detector uses scintillator pads readout by wavelength shifting fibers
that are coupled to 64 channel MaPMT (Multianode Photomultiplier) via clear plastic
fibers. MaPMT are placed at the top and at the bottom of the detector. Electronics
comprise a Very Front End (VFE) card with the fast readout electronics, a Low Voltage
(LV) distribution and monitoring card and a Control Board (CB) to connect the VFE and
LV cards to the Experiment Control System (ECS). Grounding, shielding and power
distribution is also described.

The VFE card hosts the MaPMT and performs the particle type discrimination. The
signal processing is performed by eight ASICs of eight channels each which integrate
the signal, perform pile-up compensation, and compare the level obtained to a
programmable threshold. An FPGA programmes thresholds and pile-up subtraction levels.
Four LVDS serializers send output data to the Calorimeter Front End Racks, placed on
a platform over the ECAL. The challenging requirements on distance, about 30 m for
VFE cards on SPD bottom, and on data rate, 280 Mbits/s per pair, made necessary the
development of a special method to compensate the skew. Combining this method with
frequenxcy response equalization, a high performance copper link is obtained (up to 5
Gbits/s over 30 m), using simple electronics and standard Local Area Network cables.

The LV card is based on CERN-ST Radiation Hard low drop-out regulators. The complex
power requirements of the VFE card makes necessary the use of several regulators per
card and advises monitoring to be integrated in the same board. This is done using an
FPGA which performs periodic analogue readouts of voltages and currents. LV card
also performs temperature measurements using onboard probes and probes embedded in
VFE cards.

The CB card is designed to deliver ECS interface, clock, and TFC signals to the VFE
and to LV cards. It includes an SPECS (Serial Protocol for the Experiment Control
System) mezzanine board to communicate with the ECS. It can interface up to eight VFE
or LV cards. A custom delay chip (1 ns step) performs fine phase tuning of LHC clock
for each VFE card independently. CB also participates in the level zero trigger by
computing the SPD multiplicity with the trigger data coming from PreShower Front End
card, sending the result to the trigger system in the barracks through an optical link.

Interconnection of the three sets of boards and the corresponding power supplies
turns grounding a relevant issue. The calorimeter ground configuration is a heavily
interconnected ground network (mesh structure). The main power supplies are floating
and the ground connection is done at the load (LV and VFE cards) to avoid returning
currents through the ground network. It is intended to minimize the current return
through the ground network using separated connections for ground and for the current
return (neutral conductor) of each power supply.

Primary author

David Gascon (D. ECM, Universitat de Barcelona)

Co-authors

Albert Comerma (D. ECM, Universitat de Barcelona) Alvaro Gaspar de Valenzuela (D. Electrónica, Enginyeria i Arquitectura La Salle, Universitat Ramon Llull.) Angel Dieguez (D. Electrónica, Universitat de Barcelona) Atila Herms (D. Electrónica, Universitat de Barcelona) Carlos Abellan (D. Electrónica, Enginyeria i Arquitectura La Salle, Universitat Ramon Llull.) Eduardo Picatoste (D. ECM, Universitat de Barcelona) Eugeni Grauges (D. ECM, Universitat de Barcelona) Hugo Ruiz (D. ECM, Universitat de Barcelona) Jorrdi Riera (D. Electrónica, Enginyeria i Arquitectura La Salle, Universitat Ramon Llull.) Lluis Garrido (D. ECM, Universitat de Barcelona) Mar Rosello (D. Electrónica, Enginyeria i Arquitectura La Salle, Universitat Ramon Llull.) Ricardo Graciani (D. ECM, Universitat de Barcelona) Sebastia Bota (Departament de Física. Universitat de les Illes Balears) Sebastia Tortella (D. Electrónica, Enginyeria i Arquitectura La Salle, Universitat Ramon Llull.) Sonia Luengo (D. Electrónica, Enginyeria i Arquitectura La Salle, Universitat Ramon Llull.) Xavier Vilasis (D. Electrónica, Enginyeria i Arquitectura La Salle, Universitat Ramon Llull.)

Presentation materials