Speaker
Description
Summary
The Hadronic Tile Calorimeter (TileCal) for the ATLAS experiment at LHC will send
data from 9856 channels by optical fiber links. These channels have to be read out
and processed every 10 µs by 32 Read Out Drivers (RODs) with 8 optical inputs each,
which will be placed in 4 crates, one per each calorimeter partition. With the aim
of using a common ROD motherboard in the ATLAS calorimeters, both LAr and TileCal
use the same design for their RODs. This means that the bare boards have to be
adapted for the TileCal front end electronics and dataflow requirements. In order
to adapt the boards some modifications have been done to the common design.
Firstly, hardware modifications have been done, related mainly with the reception
circuit due to the different clock frequency used in the data transmission in
TileCal and LAr. Firmware modifications have been done in the Processing Units and
the Staging FPGAs. This firmware is still being upgraded, but the versions used at
the time of production had all the functionalities needed to fully validate the
boards.
Once the RODs were adapted for TileCal, we started their validation. The test bench
mounted in TileCal laboratory at IFIC-Valencia for these tests will be described.
In this test bench we have emulated the detector front end data with the Optical
Multiplexer Board (OMB), which is able to generate events at a programmable rate
and send them to the ROD. As this board has only 2 optical outputs, an Optical
Buffer board was designed by our group in order to replicate each of these optical
fibers coming from the OMB up to 16 optical inputs to the ROD. Thus, using one OMB
and 2 Optical Buffers, it was possible to test 4 RODs at a time, which represents
half a crate.
Following, the test procedure used in order to validate each of the 38 boards (32
required units and 6 spares) will be described. The ROD production tests were
completed successfully with excellent results. At a quantitative level, more than
1.3x109 events have been processed and checked without errors, which represents a
bit error rate better than 10-14. We will present also the results obtained in G-
Link temperature monitoring studies. These components reach high temperatures while
they are powered and need continuous cooling in order to guarantee not to overheat
above the threshold recommended by the manufacturer. At a qualitative level, we
will present the results obtained regarding the reconstruction of energy, time and
χ2 in the DSPs, as well as the upgrades done at the firmware level in order to
reach a more optimized system. Once the RODs were validated in the test bench, they
were installed in the ATLAS electronics cavern (USA15), their final placement, to
read out and process data coming from the TileCal detector and participate in the
TileCal commissioning.
