Speaker
Description
Summary
TileCal is the hadronic calorimeter of the ATLAS experiments. It consists,
electronically speaking, of 10000 channels to be read each 25 ns. Data gathered
from these channels are digitized and transmitted to the data acquisition system
(DAQ) following the assertions of a three level trigger system.
In the acquisition chain, place is left for a system which has to perform pre-
processing and gathering on data coming out after a good first level trigger before
sending them to the second level. This system is called the Read Out Module (ROD).
Before the ROD we have a pre-ROD card, called Optical Multiplexed Board (OMB), able
to analyze two fibbers, both of then carrying the same data, to provide the correct
one to the ROD input.
The interest of this project was justified in February 2003, when a preliminary
study appeared. This proposal shown a solution for OMB based on exhaustive on-line
analysis of the data carried by both of the fibbers, using FPGAs for
implementation.
Universidad de Valencia – IFIC (Spain) team showed the greater interest to deal
with this project, to make a first prototype to study technical viability. In
particular, the main goals are:
• Fibber optic switching to take advantage of redundancy
• Obtain real (production) costs
• Have a development platform (hw - sw)
• Try different alternatives for data error analysis (CRC, etc.)
In this paper we want to show the Signal Integrity Studies made to this card; OMB
is a high-speed digital design and Signal Integrity has become a critical issue.
The term Signal Integrity addresses two concerns in the electrical design aspects,
the timing and the quality of the signal. The goal of this Signal Integrity
analysis is to ensure reliable high-speed data transmission.
We can divide the studies in two parts, the pre-layout (without which prototypes
may never leave the bench) and the post-layout (without which products may fail in
the field).
In the pre-layout stage, Signal Integrity analysis they were used to select
technology for I/Os, clock distributions, chip package types, component types,
board stackups, pin assignments, net topologies, and termination strategies.
With an initial physical layout, post-layout Signal Integrity analysis verified
reflection noise, ringing, crosstalk and ground bounce.
The results were correct and allowed the accomplishment of the card that at the
present time is in operation at CERN.
