Sep 25 – 29, 2006
Valencia, Spain
Europe/Zurich timezone

The LHC Beam Loss Monitoring System's Surface Building Instalation.

Sep 27, 2006, 4:20 PM
1h 40m
Valencia, Spain

Valencia, Spain

IFIC – Instituto de Fisica Corpuscular Edificio Institutos de Investgación Apartado de Correos 22085 E-46071 València SPAIN

Speaker

Christos Zamantzas (CERN)

Description

The strategy for machine protection and quench prevention of the Large Hadron Collider (LHC) at the European Organisation for Nuclear Research (CERN) is presently based on the Beam Loss Monitoring (BLM) system. At each turn, there will be several thousands of data to record and process in order to decide if the beams should be permitted to continue circulating or their safe extraction is necessary. The BLM system can be sub-divided geographically to the tunnel and the surface building installations. In this paper the surface installation is explored, focusing not only to the parts used for the processing of the BLM data and the generation of the beam abort triggers, but also to the interconnections made with various other systems in order to provide the needed functionality.

Summary

The strategy for machine protection and quench prevention of the Large Hadron
Collider (LHC) at the European Organisation for Nuclear Research (CERN) is presently
based on the Beam Loss Monitoring (BLM) system. At each turn, there will be several
thousands of data to record and process in order to decide if the beams should be
permitted to continue circulating or their safe extraction is necessary.

The BLM system can be easily sub-divided geographically to the tunnel and the surface
building installations. It consists of around 4000 detectors, placed at various
locations around the ring, tunnel electronics, which are responsible for acquiring,
digitising, and transmitting the data, and surface electronics, which receive the
data via 2km optical data links, process, analyze, store, and issue warning and abort
triggers. The later provides also the connections to the Beam Interlock, the Beam
Energy Tracking, the Logging and the Post Mortem systems. In this paper, the surface
building's electronics are explored providing details for the different parts
combined to provide the needed functionality.

This installation foresees VME crates spread over all of the eight LHC interaction
points accommodating the processing modules, a timing card, a CPU card and a Combiner
card.

The processing module is comprised by the DAB64x and the BLM Mezzanine cards. The BLM
mezzanine card handles the de-serialisation and decoding of four optical gigabit data
transmission lines in parallel. This mezzanine provides the received data to a
reconfigurable FPGA which is the backbone of the DAB64x card. Each module is able to
process in real-time up to 16 detector channels.

The timing card is the Timing Trigger and Control (TTC) card developed by the Beam
Instrumentation group. In this application it will provide the Time-Stamp and the
Post Mortem triggers.

The CPU is a PowerPC with LynxOS as operating system. Its main purpose is to access
periodically the processed data from each processing module, normalise them with
their corresponding threshold values and provide them to the Logging system before
they are displayed on the fixed displays in the control room. Moreover, it will
collect and time-stamp the Post Mortem data, stored on the circular buffers, whenever
the relevant trigger arrives.

The final receiver of the beam permit lines is the Combiner card, located at the last
slot of the crate. The two beam permit lines are daisy chained through each of the
processing modules using a custom-made backplane in the crates. If any of the
modules decides to break any of these lines a beam dump request will be given to the
LHC Beam Interlock System (BIS). As an additional use, those lines will be used by
the Combiner card to provide a continuous supervision of the operation of the cards
in the crate. Thus, it will be able to discover immediately a disconnection from the
circuit or a failure and a dump will be requested for any of those cases.

Finally, the system has been designed with reliability and availability in mind. The
processing modules can operate independently of CPU and Timing card failures. There
is redundancy in the optical transmission with additional powerful error detection.
The beam permit lines in the backplane are also redundant and the connection to the
BIS is tripled.

Primary author

Co-authors

Presentation materials