Speaker
Description
A 4-channel parallel 56 Gb/s optical receiver for VCSEL-based optical links is presented. The receiver has been manufactured in a standard 65nm-CMOS process. Simulation results with layout parasites and a model of a wire-bonded photo diode demonstrate that the single channel works at bit rate of 14 Gb/s and has an input sensitivity of better than 20 uApp, an input-referred noise of 2.3 uArms and a differential output amplitude across an external 50 ohm load of larger than 400 mVpp. The power consumption is 84 mW/channel for a power supply of 1.2 V. Test results will also be presented in the conference.
Summary
A 4-channel parallel 56 Gbit/s optical receiver is developed in a 65 nm CMOS process because the high data rate is demanded in the particle physics experiments. The receiver is designed for Vertical-Cavity Surface Emitting Laser (VCSEL) based optical links operating at 850 nm wavelength. Each channel consists of a pseudo-differential Transimpedance Amplifier (TIA), a Limiting Amplifier (LA), double Low Pass Filters (LPFs) and an output buffer. A 250 um pitch between channels is designed with the same as an off-chip photo diode array. The receiver modulation current is programmable through an I2C controller with Triple Modular Redundancy (TMR).
The TIA adopts a pseudo-differential structure to improve the power supply rejection ratio and common mode rejection ratio. A pair of CMOS inverters with resistive feedback, one active and one a replica, are used in the TIA. The TIA gain is 200 ohm. With a photo diode DC coupled to the TIA, a 2.47 uArms input-referred noise and a 25 GHz bandwidth is measured in the post-layout simulations. The power consumption of the TIA is around 7.2 mW for a power supply of 1.2 V.
The LA is a 12-stage fully differential amplifier. Interleaving active-feedback structure is adopted in the LA to extend the bandwidth for each stage. The shunt inductive peaking technique is used to extend bandwidth in the last three-stage differential amplifiers of LA at the expense of area. The simulation demonstrates that the LA has a gain of 51 dB and a bandwidth of 13.3 GHz. The LA consumes 57 mW in total for a power supply of 1.2 V.
To compensate the DC offset, double LPFs are used in each channel. The LPFs are single pole RC filters using double 210 kohm resistors and double 4.8 pF miller capacitors. Three-stage differential amplifiers with a 2.4 pF capacitor for the frequency compensation are adopted in the LPFs. The LPFs amplify the difference between the DC levels at the LA output nodes and feed back to a current mirror which generates the current source of the pseudo-differential inverted TIA to compensate the DC offset.
The output buffer driving off-chip transmission line is a differential amplifier with a load resistance of 60 ohm. The bandwidth of the output buffer is 17 GHz with a power consumption of 14.4 mW for a power supply of 1.2 V.
The 4-channel parallel 56 Gbit/s optical receiver for VCSEL-based optical links has been manufactured in a standard 65nm-CMOS process in April 2017. The receiver occupies 1.23 mm × 2 mm chip area. The simulation demonstrates that the single channel works at bit rate of 14 Gb/s, has an input sensitivity of better than 20 uApp, an input-referred noise of 2.3 uArms and a differential output amplitude across an external 50 ohm load of larger than 400 mVpp, and consumes 84 mW/channel for a power supply of 1.2 V. We expect to present the measurements in the conference in September 2017.
