Speaker
Description
- New devices (FinFETs) and fluid guardrings
- Double/ Multiple Patterning aka coloring
- Gridded/ track based placement and routing methodology
- In-design dynamic/ post-edit DRC checking to support new constraints including color and grid checks
Abstract
Continuous advancement in process technology following Moore’s law over the past few decades has greatly increased IC design complexity, not just for designers but also for EDA tools. The drive to reduce feature size beyond optical resolution of visible and ultra-violet light has led to multiple masks/ patterns for same layer to allow for a more compact layout. Need for greater scaling and manufacturing accuracy has led to a self-aligned fabrication process requiring gridded, unidirectional interconnects. At the same time, new devices such as tri-gate finFETS have been introduced to address power, leakage and variability associated with these processes. In addition to more restrictive and complex design rules for manufacturability and process characteristics, EDA tools need to account for changes in design methodology such as highly gridded placement and routing. This presentation will cover these tool enhancements and changes to meet the process technology requirements of these nodes, for both devices and interconnects, with focus on physical implementation.
