Session

TUTORIAL

15 Sept 2017, 09:30

Conveners

TUTORIAL: ASIC Design below 65 nm: Benefits and Challenges with Designing in Advanced CMOS Nodes

  • Alessandro Marchioro (CERN)

Presentation materials

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Ping Chen (Sr. Staff Application Engineer Custom IC & Simulation - Cadence Design Systems)
Oral

a. Implementation flow
b. Analysis flow

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