TWEPP 2017 Topical Workshop on Electronics for Particle Physics

Session

Programmable Logic, Design Tools and Methods

A

12 Sept 2017, 08:30

Conveners

Programmable Logic, Design Tools and Methods

• Magnus Hansen (CERN)

Programmable Logic, Design Tools and Methods

• Angelo Rivetti (Universita e INFN Torino (IT))

117. SEE Tolerant Standard Cell Based Design While Guaranteeing Specific Distance Between Memory Elements

Sandeep Miryala (Fermi National Accelerator Lab. (US))

12/09/2017, 08:30

Programmable Logic, Design Tools and Methods

Oral

Single Event Effects (SEEs) comprising of Single Event Upsets (SEUs) and Single Event Transients (SETs) corrupts the data in storage nodes/registers. Triple Modular redundancy (TMR) with clock delay insertion is a system level technique that counters SEEs in storage nodes. However, such an implementation is not straight forward in standard cell based digital design which uses cad tools like...

63. Clock and Trigger Distribution for ALICE Using the CRU FPGA Card

Jozsef Imrek (Hungarian Academy of Sciences (HU))

12/09/2017, 08:50

Programmable Logic, Design Tools and Methods

Oral

ALICE is preparing a major upgrade for 2021.

Subdetectors upgrading their counting room DAQ electronics will use a
common hardware to receive physics data: the Common Readout Unit (CRU).
The same CRU will also distribute the LHC clock and trigger to many of
the upgrading subdetectors (~7800 front end cards).

Requirements are strict: for the clock the allowed jitter (RMS) is
typically <300ps,...

89. DRM2: the Readout Board for the ALICE TOF Upgrade

Davide Falchieri (Universita e INFN, Bologna (IT))

12/09/2017, 09:10

Programmable Logic, Design Tools and Methods

Oral

For the upgrade of the ALICE TOF electronics, we have designed a new version of the readout board, named DRM2, a card able to read the data coming from the TDC Readout Module boards via VME. A Microsemi Igloo2 FPGA acts as the VME master and interfaces the GBTx link for transmitting data and receiving triggers and a low- jitter clock. Compared to the old board, the DRM2 is able to cope with...

176. FPGA Based Wireless Time Interval Measurement System with Picosecond Resolution

Mr Balaji Srinivasan (LICET)

14/09/2017, 11:05

Programmable Logic, Design Tools and Methods

Oral

We present a theoretical analysis, simulation and implementation results of an FPGA-based wireless Time Interval Measurement (TIM) system. The TIM features a single channel TDC with a Serial Peripheral Interface (SPI) and wireless transmission. The TDC is based on the Vernier ring oscillator method to achieve both high resolution and wide dynamic range. The TDC architecture with an SPI is...

131. New Slow Control FPGA IP for GBT Based Systems and Status Update of the GBT-FPGA Project

Julian Maxime Mendez (CERN)

14/09/2017, 11:25

Programmable Logic, Design Tools and Methods

Oral

The GBT-FPGA, part of the GBT project framework, is a VHDL-based IP designed to offer a back-end counterpart to the GBTX ASIC, a radiation tolerant 4.8 Gb/s optical transceiver. The GBT-SCA (Slow Control Adapter) radiation tolerant ASIC is also part of the GBT chipset and is used for the slow control in the HEP experiments. In this context, a new module named GBT-SC has been designed and...

146. Characterization and Verification Environment for the 65 nm Pixel Readout-Chip RD53A

Marco Vogt (Universitaet Bonn (DE))

14/09/2017, 11:45

Programmable Logic, Design Tools and Methods

Oral

For the Phase II Upgrade of LHC, new hybrid silicon pixel detectors are required for charged particle tracking. The RD53 collaboration is currently designing a large-scale prototype sensor readout chip “RD53A”, which will be available soon. The SiLab group at the University of Bonn is highly involved in testing/verification and several chip design tasks.

A modular and versatile test- and...