Single muon triggers are crucial for the physics programmes at hadron collider experiments. The poster presents the concept for a novel muon trigger system, which exploits data from precision chambers like drift-tube chambers. Two example implementations are provided: the future muon trigger of the ATLAS experiment at the HL-LHC and the muon trigger of the baseline detector for the FCC-hh. A...
A new ELMB (called ELMB2) is proposed for the Phase II MDT composed of new CAN bus circuitry and microprocessor replace the existing ELMB. Additionally, the current connection of the ELMB to the CSM for front-end voltage and temperature monitoring will be replaced with SCA connections to the DAQ system. The initialization of the CSM and mezzanines will also utilize the SCA connections to the...
We present an optical transmitter (MTx+) and transceiver (MTRx+) based on LC TOSA and ROSA. The transmitter uses a VCSEL driver (LOCld65) of the 65 nm CMOS technology. LOCld65 is tested up to 14 Gbps. The receiver uses the ROSA/GBTIA for the moment. The electrical connector is the same as that of a SFP+. Both MTx+ and MTRx+ receive multimode fibers with the standard LC connector. The module is...
The PiLup board has been designed by INFN and University of Bologna for a possible use in the framework of the ATLAS TDAQ system. As an improved version of the ROD for the ATLAS Pixel Read-out, it hosts two Xilinx FPGAs: A Kintex-7 featuring high throughput and heavy data-processing capability, and a Zynq-7000 equipped with an embedded System-On-Chip. The functionality and the performances of...
The upgrade of the ATLAS silicone strip detector (ITk Strips), for the HL-LHC will employ a parallel powering scheme for the bias high voltage and the low voltage electronics power. The power on a module will be managed using the Powerboard. The Poweboard uses the bPOL12V to step the external LV from 11V to 1.5V, monitor the LV and HV currents, disable power and monitor the temperature. The...
The HL-LHC ATLAS and CMS pixel detectors will be powered using a serial powering scheme, where a constant current will be provided to a chain of pixel modules powered in series. This scheme is based on the design of a Shunt-LDO regulator that has been integrated on the new RD53A prototype pixel readout chip. Two Shunt-LDO regulators, one per power domain, are used to provide the required...
The ATLAS Readout Electronics Upgrade Simulation framework (AREUS) is a detailed simulation of the LAr calorimeter readout chain, used to find optimal solutions for the analog and digital processing of the detector signals.
Simulated pulse shapes take into account effects of electronics noise and of pile-up events. Analog-to-digital conversion, gain selection and digital signal processing are...
The Daughterboard (DB) interfaces the front-end and off-detector electronics. The newest revision migrated from two QSFPs to four SFP+ modules operating at: $4 \times 9.6$ $Gbps$ uplinks handled by two Kintex Ultrascale+ FPGAs and $2 \times 4.8$ $Gbps$ downlinks handled by two GBTxs. The DB provides continuous high-speed readout of digitized PMT samples through the uplink, and receives...
We present our recent developments on an optical wavelength division multiplexed data transmission system. The nearly completed link demonstrator aims for a data rate of 4x10 Gb/s with the potential to scale the data rate up into the terabit-per-second range. Key component is a silicon-photonic chip with monolithically integrated, active and passive photonic components and circuits, whose...
The High-Luminosity LHC poses a challenge to the luminosity measurement accuracy, creating the need for the development of a new high precision online luminosity measurement system at CMS, using radiation hard detector technologies.
This work investigates the exploitation of the Tracker Endcap Pixel Extension (TEPX) for online luminosity measurement. In addition to the 750 kHz L1 physics...
In view of the installation of a prototype of the Phase-2 on-detector electronics during the long shutdown of LHC in 2018, a demonstrator of the full trigger and readout chain was built in the CMS site.It consists of a DT (Drift Tubes) chamber equipped with a single FPGA hosting 138 TDCs with 1ns resolution that timestamp the hits collected from the frontend analog discriminators. The hits are...
In the future years, luminosity, centre-of-mass energy of the proton-proton collisions at LHC will be strongly increased. Hence, next trigger system requires more challenging AM chips, with higher processing capability, lower power consumption, and higher memory density.
This work describes the characterization work on the first prototype (AM07) of these new generation 28 nm AMchips. ...