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ACES 2018 - Sixth Common ATLAS CMS Electronics Workshop for LHC Upgrades

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80/1-001 - Globe of Science and Innovation - 1st Floor (CERN)

80/1-001 - Globe of Science and Innovation - 1st Floor

CERN

60
Show room on map
Magnus Hansen (CERN), Philippe Farthouat (CERN)
Description

This workshop will be dedicated to electronic issues for upgrades, focusing on subjects where common features or developments are likely. Developments for upgrades for proton-proton and heavy ion running for Phase I and for high luminosity LHC (HL-LHC) will be included.

The following main areas will be covered:

  • Front-end electronics developments for Phase I and HL-LHC
  • Electronics systems for triggering at Phase I and HL-LHC, including level-1 tracking trigger and the use of modular electronics standards such as xTCA
  • Electronics systems for DAQ and DCS at HL-LHC
  • High precision timing measurement and clock distribution systems
  • Optical and electrical links
  • Power distribution and low power design techniques
  • IC technologies and radiation hardness issues
  • Progress on upgrades for HL-LHC

The oral presentations will be made by invitation. A poster session will be organised for which abstracts will have to be submitted on the indico page. More details can be obtained in contacting a member of the Programme Committee:

  • Didier Contardo (LYON)
  • Kevin Einsweiler (LBL)
  • Philippe Farthouat (CERN)
  • Cristina Fernandez (CIEMAT)
  • Alex Grillo (UCSC)
  • Magnus Hansen (CERN)
  • Jeroen Hegeman (CERN)
  • Oliver Kortner (MPI)
  • Francesco Lanni (BNL)
  • Alessandro Marchioro (CERN)
  • Arno Straessner (DRESDEN)
  • Francois Vasey (CERN)
  • Administrative assistance provided by Evelyne Dho (CERN)

Registration is free (except for the conference dinner), but participants must register online before

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  • Tuesday 24 April
    • Posters (from Tuesday am to Thursday pm) 80/1-001 - Globe of Science and Innovation - 1st Floor

      80/1-001 - Globe of Science and Innovation - 1st Floor

      CERN

      60
      Show room on map
      • 1
        First-Level Muon Track Trigger for Future Hadron Collider Experiments

        Single muon triggers are crucial for the physics programmes at hadron collider experiments. The poster presents the concept for a novel muon trigger system, which exploits data from precision chambers like drift-tube chambers. Two example implementations are provided: the future muon trigger of the ATLAS experiment at the HL-LHC and the muon trigger of the baseline detector for the FCC-hh. A detailed description of fast-track reconstruction algorithms is also provided. The baseline system is based on the use of modern FPGA technology with an embedded microprocessor for floating point operations (System-on-Chip).

        Speaker: Davide Cieri (Max-Planck-Institut fur Physik (DE))
        poster-aces-2018-dcieri.pdf
      • 2
        Proposed Phase II ELMB for MDT Upgrade

        A new ELMB (called ELMB2) is proposed for the Phase II MDT composed of new CAN bus circuitry and microprocessor replace the existing ELMB. Additionally, the current connection of the ELMB to the CSM for front-end voltage and temperature monitoring will be replaced with SCA connections to the DAQ system. The initialization of the CSM and mezzanines will also utilize the SCA connections to the front-end which will decouple the startup and recovery of the MDT from the DCS system.

        Speaker: Jay Chapman (University of Michigan (US))
        ELMB Poster v4.jpg
      • 3
        Optical transmitter (MTx+) and transceiver (MTRx+)

        We present an optical transmitter (MTx+) and transceiver (MTRx+) based on LC TOSA and ROSA. The transmitter uses a VCSEL driver (LOCld65) of the 65 nm CMOS technology. LOCld65 is tested up to 14 Gbps. The receiver uses the ROSA/GBTIA for the moment. The electrical connector is the same as that of a SFP+. Both MTx+ and MTRx+ receive multimode fibers with the standard LC connector. The module is 6 mm in height and can be panel or board mounted. Measurement results will be present. MTx+ and MTRx+ with evaluation boards can be obtained for further development.

        Speaker: Jingbo Ye (Southern Methodist University, Department of Physics)
        Poster_Jingbo_MTxPlus.pdf
      • 4
        The PiLup board: functionality, performances and potential application.

        The PiLup board has been designed by INFN and University of Bologna for a possible use in the framework of the ATLAS TDAQ system. As an improved version of the ROD for the ATLAS Pixel Read-out, it hosts two Xilinx FPGAs: A Kintex-7 featuring high throughput and heavy data-processing capability, and a Zynq-7000 equipped with an embedded System-On-Chip. The functionality and the performances of the more up-to-date prototype will be described. As an example of potential application, tests to interface a RD53 pixel emulator and the ATLAS Felix board will be shown.

        Speaker: Dr Riccardo Travaglini (INFN, Bologna (IT))
        Poster-Travaglini-PiLup_v2.pdf
      • 5
        The ITk Strips Powerboard (v2) for The ATLAS Barrel

        The upgrade of the ATLAS silicone strip detector (ITk Strips), for the HL-LHC will employ a parallel powering scheme for the bias high voltage and the low voltage electronics power. The power on a module will be managed using the Powerboard. The Poweboard uses the bPOL12V to step the external LV from 11V to 1.5V, monitor the LV and HV currents, disable power and monitor the temperature. The last three tasks are accomplished using the AMAC chip. This poster will present the design of Powerboard v2, initial test results and the plans for the production of the O(10,000) required Powerboards.

        Speaker: Karol Krizka (Lawrence Berkeley National Lab. (US))
        powerboard.pdf
      • 6
        Serial powering testing with the 2.0A Shunt-LDO regulator of the RD53A pixel readout chip

        The HL-LHC ATLAS and CMS pixel detectors will be powered using a serial powering scheme, where a constant current will be provided to a chain of pixel modules powered in series. This scheme is based on the design of a Shunt-LDO regulator that has been integrated on the new RD53A prototype pixel readout chip. Two Shunt-LDO regulators, one per power domain, are used to provide the required voltages while shunting any extra provided current. This poster presents results on the characterization of the 2.0A Shunt-LDO regulator and testing of the new RD53A pixel chips serially powered.

        Speaker: Dominik Koukola (Vienna University of Technology (AT))
        Koukola_SerialPowerTesting_Poster_ACES.pdf
      • 7
        AREUS - a software framework for ATLAS Readout Electronics Upgrade Simulation

        The ATLAS Readout Electronics Upgrade Simulation framework (AREUS) is a detailed simulation of the LAr calorimeter readout chain, used to find optimal solutions for the analog and digital processing of the detector signals.
        Simulated pulse shapes take into account effects of electronics noise and of pile-up events. Analog-to-digital conversion, gain selection and digital signal processing are modeled at bit precision, including digitization noise and detailed electronics effects. Signal processing techniques can be optimized with respect to physics parameters like reconstructed energy and signal time in each channel. Trigger and object reconstruction algorithms can be integrated in the optimization process.

        Speaker: Philipp Horn (Technische Universitaet Dresden (DE))
      • 8
        Redesign of the ATLAS hadronic Tile Calorimeter read out link and control board (Daughterboard) for the Phase-2 upgrade heading towards the High Luminosity Large Hadron Collider.

        The Daughterboard (DB) interfaces the front-end and off-detector electronics. The newest revision migrated from two QSFPs to four SFP+ modules operating at: $4 \times 9.6$ $Gbps$ uplinks handled by two Kintex Ultrascale+ FPGAs and $2 \times 4.8$ $Gbps$ downlinks handled by two GBTxs. The DB provides continuous high-speed readout of digitized PMT samples through the uplink, and receives configuration, control and LHC synchronized timing through the downlink. TMR, FEC and CRC strategies, plus a double redundant design, aimed to virtually eliminate all possible single failure points and withstand damage from minimum ionizing and hadronic radiation, as well as single-event upsets.

        Speaker: Mr Eduardo Valdes Santurio (Stockholm University (SE))
        ATL-COM-UPGRADE-2018-007.pdf
      • 9
        Silicon photonic wavelength division multiplexed high-speed links

        We present our recent developments on an optical wavelength division multiplexed data transmission system. The nearly completed link demonstrator aims for a data rate of 4x10 Gb/s with the potential to scale the data rate up into the terabit-per-second range. Key component is a silicon-photonic chip with monolithically integrated, active and passive photonic components and circuits, whose characteristics will be shown.

        Speaker: Dr Marc Schneider (Karlsruhe Institute of Technology)
        ACES2018-Workshop_Schneider_SiliconPhotonics_IndicoVersion.pdf
      • 10
        High Precision Online Luminosity Measurement using the CMS Phase 2 Upgrade of the Inner Tracker

        The High-Luminosity LHC poses a challenge to the luminosity measurement accuracy, creating the need for the development of a new high precision online luminosity measurement system at CMS, using radiation hard detector technologies.
        This work investigates the exploitation of the Tracker Endcap Pixel Extension (TEPX) for online luminosity measurement. In addition to the 750 kHz L1 physics trigger, an extra 75 kHz of trigger bandwidth from the TEPX will be allocated for luminosity. This accounts for about 110 Gb/s of acquired data that need processing in a dedicated back end system, using real-time implementations of algorithms for luminosity measurement.

        Speaker: Mr Alexander Ruede (CERN/KIT-IPE)
        Ruede_ACES_2018.pdf
      • 11
        The Drift Tubes Test Stand for Phase-2 Upgrade

        In view of the installation of a prototype of the Phase-2 on-detector electronics during the long shutdown of LHC in 2018, a demonstrator of the full trigger and readout chain was built in the CMS site.It consists of a DT (Drift Tubes) chamber equipped with a single FPGA hosting 138 TDCs with 1ns resolution that timestamp the hits collected from the frontend analog discriminators. The hits are then moved through high-speed links (10Gbps) towards the backend that is responsible for buffering the data and trigger generation.

        Speaker: Andrea Triossi (Centro de Investigaciones Energéti cas Medioambientales y Tecno)
        SX5_ACES18.pdf
      • 12
        AM07: Characterization of the Novel Associative Memory Chip Prototype Designed in 28 nm CMOS Technology for High Energy Physics and Interdisciplinary Applications

        In the future years, luminosity, centre-of-mass energy of the proton-proton collisions at LHC will be strongly increased. Hence, next trigger system requires more challenging AM chips, with higher processing capability, lower power consumption, and higher memory density.

        This work describes the characterization work on the first prototype (AM07) of these new generation 28 nm AMchips. Characterization results confirm the chip functionality up to 200 MHz as expected in simulation. With respect to the 65 nm AM06 chip, we achieved interesting results: we reduced the power consumption by a factor of 1.7 and the silicon area by a factor of 2.9.

        Speaker: Giacomo Fedi (Universita & INFN Pisa (IT))
        2018 Poster ACES-final_reduced.pdf
    • Upgrades Overview 80/1-001 - Globe of Science and Innovation - 1st Floor

      80/1-001 - Globe of Science and Innovation - 1st Floor

      CERN

      60
      Show room on map
      Convener: Magnus Hansen (CERN)
    • 10:30
      Coffee break 80/1-001 - Globe of Science and Innovation - 1st Floor

      80/1-001 - Globe of Science and Innovation - 1st Floor

      CERN

      60
      Show room on map
    • IC Technology 80/1-001 - Globe of Science and Innovation - 1st Floor

      80/1-001 - Globe of Science and Innovation - 1st Floor

      CERN

      60
      Show room on map
      Convener: Francois Vasey (CERN)
    • 12:35
      Lunch
    • 16:00
      Coffee break 80/1-001 - Globe of Science and Innovation - 1st Floor

      80/1-001 - Globe of Science and Innovation - 1st Floor

      CERN

      60
      Show room on map
    • Timing 80/1-001 - Globe of Science and Innovation - 1st Floor

      80/1-001 - Globe of Science and Innovation - 1st Floor

      CERN

      60
      Show room on map
      Convener: Francesco Lanni (Brookhaven National Laboratory (US))
  • Wednesday 25 April
  • Thursday 26 April
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