Speaker
Alessandro Gabrielli
(INFN Bologna and Physics Department)
Description
A fast readout architecture with sparsification capabilities for a 256-pixel 3D ASIC was recently proposed by the Italian VIPIX Collaboration and submitted to the CMOS Chartered 130 nm technology. In particular, the readout logic exploits one of the two layers of a 3D device. The readout logic allows sweeping the matrix within 1us and can face an input hit-rate of 100MHz/cm2. The architecture has been deeply investigated in terms of efficiency and sparsification capabilities and a parameterized Register-Transfer-Logic VHDL code has been designed. The paper presents the readout efficiency versus a variety of parameters as the clock rate, the pixel hit-rate and the time-stamp resolution. In addition, the study shows how the readout layer might be adapted to future larger matrices of pixels. A fast readout might also match a data-driven tracking system. The overall project leads to design a high-density thin vertex detector with an on-chip sparsified digital readout system, for particle tracking, aimed at matching the requirements of future high-energy physics experiments.
Author
Alessandro Gabrielli
(INFN Bologna and Physics Department)
