WIT2010 Workshop on Intelligent Trackers

Session

Electronic circuits (3D and conventional)

4 Feb 2010, 14:00

Perseverance Hall (Lawrence Berkeley National Lab)

24. Application of Vertically Integrated Electronics to Intelligent Trackers

Dr Ronald Lipton (Fermi National Accelerator Lab. (Fermilab))

04/02/2010, 14:00

Electronic circuits (3D and conventional)

Oral presentation

At Super-LHC luminosity it is expected that the standard suite of L1 triggers for CMS will saturate. Information from the tracker will be needed to reduce trigger rates to satisfy the L1 bandwidth. Tracking trigger modules which correlate information from closely-spaced sensor layers to form an on-detector momentum filter are being developed by several groups. We report on a trigger module...

27. Fast Readout Logic Interfacing a 256-Pixel Matrix of a Dual-Layer 3D Device

Alessandro Gabrielli (INFN Bologna and Physics Department)

04/02/2010, 14:30

Electronic circuits (3D and conventional)

Oral presentation

A fast readout architecture with sparsification capabilities for a 256-pixel 3D ASIC was recently proposed by the Italian VIPIX Collaboration and submitted to the CMOS Chartered 130 nm technology. In particular, the readout logic exploits one of the two layers of a 3D device. The readout logic allows sweeping the matrix within 1us and can face an input hit-rate of 100MHz/cm2. The architecture...

36. Present and future inter pixel communication architectures in Timepix/Medipix derived read out chips

Mr Xavier Llopart Cudie (CERN)

04/02/2010, 15:00

Electronic circuits (3D and conventional)

Oral presentation

The Medipix3 read out chip (ROC) demonstrates the successful use of inter-pixel communication to reconstruct spectroscopic information from X-ray hits in a segmented sensor mitigating the effects of charge sharing. Building on this work and the success of the current Timepix chip, conceptual designs for the matrix architecture of the Timepix2 and VELOpix ROCs are presented. These chips will...

14. Towards a high performance vertex detector based on 3D integration of Deep N-Well MAPS

Valerio Re (INFN)

04/02/2010, 15:30

Electronic circuits (3D and conventional)

Oral presentation

The development of deep N-well (DNW) CMOS active pixel sensors was driven by the ambitious goal of designing a monolithic device with similar functionalities as in hybrid pixel readout chips, such as pixel-level sparsification and time stamping. The implementation of the DNW MAPS concept in a 3D vertical integration process naturally leads the designer towards putting more intelligence in the...