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Description
This paper presents a Fast-Tracker front-end (FTfe) for small-diameter Muon Drift Tube (sMDT) detectors at future hadron colliders. The design addresses the higher background rate capability required by the sMDT detectors, which needs to be complemented by suitable front-end electronics. sMDT chambers operate at short maximum drift time and, consequently, short dead-time, maximizing the muon detection efficiency. FTfe ensures fast baseline restoration with a reset interval of maximum 160ns, such that muon pulses are not distorted or even masked by preceding background pulses. The device has been designed in 1V-28nm-CMOS technology with 0.03mm2 of area, 4.7mV/fC sensitivity and 0.24fC ENC.
Summary
The high luminosity and interaction rates at future hadron colliders like HL_LHC and the FCC-hh pose challenging requirements for detectors and read-out electronics. Ultra-scaled ICs can be exploited in HEP (High-Energy-Physics) applications to design front-ends with higher speed and resolution and lower area, maintaining good performance.
The read-out electronics used in the current MDT chambers of the ATLAS detector at the LHC consists of ASD (Amplification-Shaper-Discriminator) blocks to extract charge arrival time and amplitude information, followed by TDCs for digital conversion. In order to avoid baseline shift at high counting rates, bipolar shaping has been adopted for the ATLAS MDT front-end. The ionization clusters in the drift tube arriving at the sense wire cause multiple threshold crossings for each muon track, increasing the data volume. As the transmission bandwidth is limited, the dead-time of the readout electronics is artificially adjusted to be longer than the maximum drift time, about 820ns.
The small-diameter MDT (sMDT) chambers, for which the proposed front-end has been designed, have 15mm instead of 30mm diameter drift tubes and, consequently, much shorter maximum drift-time (~180 ns) than the MDT chambers. Therefore, sMDTs can offer about 10 times higher rate capability if also the readout electronics is optimized for the even higher background rates at future hadron colliders. With the reduced dead-time, which improves the muon detection efficiency at high rates, pile-up effects of the muon signals on top of the bipolar undershoots of preceding background pulses become significant, reducing the efficiency and also the time/spatial resolution.
The Fast-Tracker front-end (FTfe) presented here employs a front-end reset and reduced dead-time in order to further improve efficiency and spatial resolution of sMDT chambers. Integrated in 28nm-bulk-CMOS technology (one of the first devices for this application in this node), FTfe starts with a Charge-Sensitive-Amplifier (CSP), composed by a single-ended opamp with feedback capacitor CF, resistor RF and switch SW for reset. The following Active-Gm-RC filter performs amplification and unipolar shaping for tail cancellation. Then the shaper output is compared with two different thresholds so that arrival time and charge amplitude information are extracted directly during the rising edge. Soon after, a logic block generates a proper reset signal for SW, CF is discharged and CSP output is restored quickly at the baseline voltage. During the short reset interval, the front-end is blind at any other pulse. As soon as the reset signal is disabled, the front-end returns to detect correctly the next incoming hit, because no pile-up occurs.
Post-layout simulations validate the proposed architecture, with relevant performance as a peaking time delay of 28 ns, sensitivity of 4.7 mV/fC and ENC of 0.24 fC, all measured at the Shaper output. The resulting dead-time of maximum 160 ns is less than the maximum drift-time, improving further the sMDT efficiency. Preliminary measurements with consecutive hits at the input, reproducing the sMDT, confirm that during the reset interval, the front-end does not elaborate any incoming hit, but only the primary pulse is read. Power consumption is 1.9 mW at 1V of supply voltage.
