Ethernet-based slow control system for parallel configuration of FPGA-based front-end boards

18 Sept 2018, 17:20
1h 30m
FBS 0.01/0.02 (Feestzaal)

FBS 0.01/0.02 (Feestzaal)

Poster Programmable Logic, Design Tools and Methods Posters

Speaker

Dr Wojciech Zabołotny (Institute of Electronic Systems, Warsaw University of Technology)

Description

The Ethernet network is a good control interface for distributed measurement systems.
The de facto standard in HEP experiments is IPbus. The experiences from using IPbus resulted in the proposal of a new Ethernet-based control interface optimized for quick parallel configuration of multiple systems.
The system ensures reliable delivery of control commands and responses.
The minimalistic local controller minimizes the negative effects of the Ethernet round-trip latency.
Usage of layer 2 Ethernet frames minimizes the FPGA resource consumption.
Implementation of the software part in Linux kernel space reduces dependency on specific software packages and libraries.

Summary

Usage of Ethernet to control the FPGA-based electronics from PC is not a new idea. The EtherBone was an attempt to extend the WishBone bus through the Ethernet but wasn't widely accepted.
The IPbus is a successful system used to control front-end electronics (FE) via the IP network.
Despite big success of the IPbus, it seems that there are certain areas for improvement.
In most scenarios, the IPbus must be used with Control Hub located near to the controlled device to ensure reliable delivery of IP packets.
The proposed solution eliminates the additional IP layer, using the Ethernet frames to minimize the FPGA resources usage.
The solution ensuring the reliable delivery of frames is implemented in the Linux kernel driver at the End Controller, eliminating complex library dependencies of the Control Hub.
The resource consumption in the End Controller is minimal, so even a simple network router with open source Linux firmware may be used to control multiple FE boards.
The communication between the End Controller and machines executing the control algorithms (User Controllers) is provided by ZeroMQ protocol.
The End Controller may be asynchronously notified about the hardware events in the FE, and further User Controllers may be informed about such "interrupts" using the ZeroMQ Publish/Subscribe mechanism.
The ZeroMQ traffic may be passed via encrypted channels allowing secure control via unprotected network.
To speed up the parallel configuration of the multiple FE boards, the FPGA controller core can execute the whole list of the commands stored in the Ethernet frame. The similar functionality is available in IPbus via accumulating multiple commands before issuing the "dispatch" command.
However, the proposed solution allows autonomous performing locally at the FE the low-level handshake tasks, e.g., waiting with timeout for certain bits to be set or cleared.
Errors occurring during the execution of such lists are reported, allowing the user software to perform the necessary cleanup or retry routine.
The above solution significantly eliminates negative consequences of the long round-trip latency typical for Ethernet-based control interfaces.
The proposed solution may control different local FPGA buses like WishBone or AXI4-Lite.
The local FPGA controller may also be adapted for operation with other than Ethernet transport layers.
Of course, the proposed solution is not mature yet, but may bring and some new ideas to the technology of Ethernet-based control of distributed systems.

Author

Dr Wojciech Zabołotny (Institute of Electronic Systems, Warsaw University of Technology)

Presentation materials

Peer reviewing

Paper