TWEPP 2018 Topical Workshop on Electronics for Particle Physics

Session

Trigger

18 Sept 2018, 14:25

Conveners

Trigger

• Gregory Michiel Iles (Imperial College (GB))

Trigger

• Ken Wyllie (CERN)

Trigger

• Marcus Julian French (Science and Technology Facilities Council STFC (GB))

165. NaNet: a Reconfigurable PCIe Network Interface Card Architecture for Real-time Distributed Heterogeneous Stream Processing in the NA62 Low Level Trigger.

Paolo Cretaro (INFN - National Institute for Nuclear Physics)

18/09/2018, 14:25

Trigger

Oral

The NA62 experiment at CERN SPS is aimed at measuring the branching ratio of the very rare kaon decay K+-> pi+ nu nubar.
NaNet is the reconfigurable design of a FPGA-based PCI Express Network Interface Card with processing, RDMA and GPUDirect capabilities and support for multiple link technologies.
NaNet has been employed to implement a real-time distributed processing pipeline in the low...

152. ALICE trigger system for LHC Run 3

Marian Krivda (University of Birmingham (GB))

18/09/2018, 14:50

Trigger

Oral

The ALICE Central Trigger Processor (CTP) will be upgraded for LHC Run 3 with completely new hardware and a new Trigger and Timing System (TTS) based on a Passive Optical Network (PON) system. A new universal trigger board was designed which can function as a CTP or as a LTU. It is based on the Xilinx Kintex Ultrascale FPGA and upgraded TTC-PON. The new trigger system and the results of the...

3. HLS4ML: deploying deep learning on FPGAs for L1 trigger and Data Acquisition

Javier Mauricio Duarte (Fermi National Accelerator Lab. (US))

19/09/2018, 11:35

Trigger

Oral

Machine learning is becoming ubiquitous across HEP. There is great potential to improve trigger and DAQ performances with it. However, the exploration of such techniques within the field in low latency/power FPGAs has just begun. We present HLS4ML, a user-friendly software, based on High-Level Synthesis (HLS), designed to deploy network architectures on FPGAs. As a case study, we use HLS4ML...

85. The Muon to Central Trigger Processor Interface for the Upgrade of the ATLAS Muon Trigger for Run-3

Marcos Vinicius Silva Oliveira (Federal University of Juiz de Fora (BR))

19/09/2018, 12:00

Trigger

Oral

The Muon-to-Central Trigger Processor Interface(MUCTPI) of the Level-1 muon trigger of the ATLAS experiment is being replaced for the LHC Run-3. The upgraded MUCTPI is implemented as an ATCA module using high-end FPGAs and high-density ribbon fibre-optic modules to integrate over 270 multi-gigabit optical inputs and outputs on a single board.
The MUCTPI also features a System-on-Chip(SoC) with...

65. Hardware Trigger Processor for the ATLAS NSW System

Thiago Costa De Paiva (University of Massachusetts (US))

19/09/2018, 14:00

Trigger

Oral

The main goals of the ATLAS New Small Wheel (NSW) upgrade are to reduce fake triggers from backgrounds hits and improve the tracking efficiency in the high rate environment at the LHC. A low-latency hardware trigger processor is being developed for the NSW in the muon spectrometer. The processor will fit candidate muon segments in the small-strip Thin Gap (sTGC) and MicroMegas (MM) chambers in...

63. Jets and topological trigger selection performed with the last generation Xilinx FPGA

Marek Palka (Jagiellonian University (PL))

19/09/2018, 14:25

Trigger

Oral

For LHC Run3, ATLAS is planning a major detector and trigger upgrade. The new Feature EXtractors (FEXs) system will allow to reconstruct different physics objects for the Level-1 calorimeter trigger selection. This includes a Jet FEX, which will identify small/large area jets and MET.
An upgraded L1 Topological Processor will allow to select interesting physics events applying topological...

25. Serenity - An ATCA prototyping platform for CMS Phase-2

Dr Andrew Rose (Imperial College London)

19/09/2018, 14:50

Trigger

Oral

Serenity is an ATCA prototyping platform designed to explore alternative, novel design choices for CMS Phase-2. It uses a newly available interconnect technology from Samtec (z-ray) to mount a removable processing unit (FPGA) that should mitigate risk and provides significant flexibility in processing unit choice and connectivity. The presentation will explore the pros and cons of using an...