18-22 February 2019
Vienna University of Technology
Europe/Vienna timezone

Deep Machine Learning on FPGAs for L1 trigger and Data Acquisition

Not scheduled
15m
Vienna University of Technology

Vienna University of Technology

Gusshausstraße 27-29, 1040 Wien
Board: 69
Poster Electronics Poster Session B

Speaker

Sioni Paris Summers (Imperial College Sci., Tech. & Med. (GB))

Description

Machine learning is becoming ubiquitous across HEP. There is great potential to improve trigger and DAQ performances with it. However, the exploration of such techniques within the field in low latency/power FPGAs has just begun. We present HLS4ML, a user-friendly software, based on High-Level Synthesis (HLS), designed to deploy network architectures on FPGAs. As a case study, we use HLS4ML for boosted-jet tagging with deep networks at the LHC. We map out resource usage and latency versus network architectures, to identify the typical problem complexity that HLS4ML could deal with. We discuss possible applications in current and future HEP experiments.

Primary authors

Sergo Jindariani (Fermi National Accelerator Lab. (US)) Nhan Viet Tran (Fermi National Accelerator Lab. (US)) Maurizio Pierini (CERN) Jennifer Ngadiuba (CERN) Javier Mauricio Duarte (Fermi National Accelerator Lab. (US)) Ben Kreis (Fermi National Accelerator Lab. (US)) Philip Coleman Harris (Massachusetts Inst. of Technology (US)) Zhenbin Wu (University of Illinois at Chicago (US)) Edward Kreinard (HawkEye360) Song Han (MIT) Sioni Paris Summers (Imperial College Sci., Tech. & Med. (GB))

Presentation Materials

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