Nov 4 – 8, 2019
Adelaide Convention Centre
Australia/Adelaide timezone

New Jet Feature Extraction and Topological Processor modules for ATLAS Phase-I Upgrade: from design to commissioning

Nov 7, 2019, 2:45 PM
15m
Riverbank R5 (Adelaide Convention Centre)

Riverbank R5

Adelaide Convention Centre

Oral Track 1 – Online and Real-time Computing Track 1 – Online and Real-time Computing

Speaker

Christian Kahra (Johannes Gutenberg Universitaet Mainz (DE))

Description

To cope with the enhanced luminosity at the Large Hadron Collider (LHC) in 2021, the ATLAS collaboration is planning a major detector upgrade to be installed during the Long shutdown 2 (LS2). As a part of this, the Level 1 trigger, based on calorimeter data, will be upgraded to exploit the fine granularity readout using a new system of Feature EXtractors (FEX) and a new Topological Processor (L1Topo) that will process the Trigger Objects (TOBs) sent by FEXs and L1Muon, selecting interesting physics events by applying kinematic and angular requirements on muons, electromagnetic clusters, jets and total energy.

The jet Feature Extractor (jFEX) has been conceived to identify small/large area jets, large-area tau leptons, missing transverse energy and the total sum of the transverse energy. It will exploit and process the data with a granularity of 0.1 x 0.1 in (eta,phi) sent at 11.2 Gb/s from the calorimeters and sort into TOBs using dedicated algorithms with a VHDL description. The TOBs will be transmitted then at 12.8 Gb/s to the L1Topo via optical links.

The L1Topo system has been initially introduced in Run 2 to improve the trigger performance by correlating trigger objects, such as electromagnetic clusters, jets and muons, and global quantities. The system performs topological calculations on the first trigger stage, for example invariant or transverse mass cuts, angular cuts or jet energy sums. During LS2, upgraded L1Topo modules will be installed benefiting from a larger processing power available for the implemented algorithms. The jFEX and L1Topo modules exploit the latest generation of the Xilinx Ultrascale+ FPGA, XCVU9P-2FLGA2577E, characterized by large input bandwidth, up to ~ 3Tb/s per module, and large processing power.

This contribution focuses on the design characteristics of L1Topo and jFEX and the test results performed on the L1Topo and jFEX prototypes. Both systems will be produced by Autumn 2019 to allow for completion of installation and commissioning before LHC restarts in March 2021.

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Primary authors

Christian Kahra (Johannes Gutenberg Universitaet Mainz (DE)) Savanna Marie Shaw (University of Manchester)

Presentation materials