Speaker
Description
For the Phase-2 upgrade of ATLAS and CMS tracking detectors, a new pixel readout chip, with 50x50 um2 pixel pitch, is being designed in 65 nm CMOS technology by the RD53 collaboration. A large-scale demonstrator chip called RD53A, containing design variations in the pixel matrix, among which three different analog front ends, is now available. A dedicated program of testing and detailed characterization has been devised and carried out to qualify the three front ends in terms of key performance parameters for the operation of a pixel detector at HL-LHC.
Summary
The Phase-2 upgrades of silicon pixel detectors at HL-LHC experiments will have to cope with extreme operating conditions, such as unprecedented radiation levels and high hit and trigger rates. In order to face such challenging requirements, a new generation of pixel readout chip is being designed in 65 nm CMOS technology, thanks to a joint effort between ATLAS and CMS, called RD53 collaboration.
As an intermediate step towards the final implementation, a large-scale demonstrator chip has been designed and called RD53A. The chip size is 20.0 mm by 11.8 mm and the pixel matrix is composed of 400 x 192 pixels, with 50 x 50 um2 pixel pitch. RD53A is not intended to be a production IC for use in an experiment, since it contains design variations in the pixel matrix, among which three different analog front ends.
An analog front end is one of the most crucial parts of a readout chip, as it collects the signal directly from the detector and translates it into the digital world. In the RD53A chip three substantially different analog front-end flavors, designed independently, were implemented. They are called linear, differential and synchronous front end. All three of them have the same calibration injection circuit and use the time-over-threshold technique, to provide a measurement of the signal amplitude.
All three front ends (FE) are based on a charge-sensitive amplifier. The linear and the synchronous FE use a krummenacher circuit for the feedback loop, featuring also the leakage current compensation, while the differential uses a simple MOS in the feedback for continuous reset and a low-pass filter for the leakage current compensation. Moreover, the differential FE uses a differential gain stage in front of the discriminator and implements a threshold by unbalancing the two branches. Both linear and differential FEs have a time-continuous discriminator with per-pixel trimming DAC for threshold tuning. The synchronous FE has a synchronous discriminator and is using an innovative technique, called autozeroing, consisting in a periodic acquisition of the baseline to avoid the need of trimming DACs. Finally, while the linear and differential FEs use the master 40 MHz clock to measure the time over threshold, the synchronous one can optionally use a local oscillator as a fast clock.
In this talk we will present the dedicated testing program established to qualify the three front ends in terms of key performance parameters, such as low threshold operation and threshold dispersion, preamplifier speed, power consumption, noise occupancy and time response. This testing program is expected to allow the CMS collaboration to choose the design of the front-end amplifier for the production readout chip, well before the TWEPP conference, and therefore the most relevant test results leading to this choice (performed on chips bonded to sensors and operated at cold temperature) will be presented.
