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Description
ALTIROC2 is an ASIC designed to readout a pixel matrix of 15 x 15 Low Gain Avalanche Diodes (LGAD) for the High-Granularity Timing Detector in ATLAS. It measures the TOT and TOA with a resolution of tens of ps for each detected hit. Data are temporally stored in a buffer able to cope with latencies up to 35µs. The ASIC also measures the luminosity of each bunch crossing with two different time windows. Timing and luminosity data are transmitted through two high speed e-links at different rates, depending on the radial position of the ASIC in the detector.
Summary
The increase of pileup will be one of the main challenges in the High-Luminosity LHC. A way to mitigate the effects of the pileup is the use high precision timing information to distinguish between collisions very close in space but well separated in time. A High-Granularity Timing Detector (HGTD) has been proposed for the ATLAS Phase II Upgrade. The detector will be made of hybrid pixels based on Low Gain Avalanche Diode (LGAD) technology.
ALTIROC2 is an ASIC designed to readout modules of 15 x 15 pixels of 1.3 x 1.3 mm2. Each pixel includes an analog front end stage composed of preamplifier, discriminator with a 4-bits DAC to fine tune the threshold level, and two Time to Digital Converters (TDC). The latter will provide the Time Of Arrival (TOA) and the Time Over Threshold (TOT) with a precision of 20 ps. The on-pixel digital electronics include a buffer to store temporally the data generated in each bunch crossing and able to cope with latencies up to 35µs, and a windowing circuit to measure the luminosity. They perform zero-suppression and keep the data on pixel are readout by the electronics on the periphery.
ALTIROC2 receives 8-bits fast commands from the central Trigger Data Acquisition system (TDAQ). This also sources a 320 MHz clock signal, from which an internal 40 MHz clock is generated. Based on this, a phase-locked loop (PLL) produce all the different internal clocks needed to operate the ASIC. A phase shifter aligns the phase of all internal clocks with an accuracy of 100 ps.
The fast commands are processed by a control unit that handles the readout of the pixel matrix. It includes a 12-bits bunch crossing counter to generate a bunch crossing identifier (BCID) and a trigger table to store trigger events. When an L0/L1 accept command is received by the ASIC, the control unit generates an internal trigger signal and a trigger identifier (TrigID) and then they are passed to all the pixels. The TrigID stored with the corresponding BCID in the table. Upon receiving the trigger signal, the control unit retrieves and store the data from the pixels related to the trigger bunch crossing. Then the data are moved into the Hit Data Formatting module, where they are packed in frames, serialised and transmitted to the peripheral on-detector electronics through e-links. The transmission speed of the e-link will depend on the radial position of the ASIC, and will be set via and Inter-Integrated Circuit bus I2C to one of three values: 320 Mb/s, 640 Mb/s and 1.28 Gb/s. The I2C is also used to configure the ASIC.
Another function of ALTIROC2 is to measure the luminosity of each bunch crossing. It sums the 225 luminosity outputs, hit or not, over two time windows of different length centred on the bunch crossing. Both sums are processed and the transferred to the luminosity serializer where are packed in frames and transmitted at 640 MHz through an e-link.
