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Description
SAR converters are usually the natural choice to implement monitoring ADCs. Additional circuits for calibration are needed to compensate process variations which become more important for large resolutions and deep-submicron technologies. This paper presents a 12-bits second-order incremental sigma delta converter for TimePix4 fabricated in TSCM 65nm. It does not need calibration and is robust to process variations because most of the signal processing is performed in the digital domain. It provides a maximum conversion rate of 1kHz/s, enough for monitoring the internal signals of the chip, consuming only 8µW. Simulations show a SNR of 84.9dB operating in free-running mode.
Summary
Delta-sigma converters offer high resolution at moderate speeds and present low sensitivity to process variations because a significant amount of the signal processing is performed in the digital domain. This robustness to process variations is an important feature nowadays, where the use of deep submicron processes is generalized and parameter spread is more significant in each new technological node. It was decided to exploit this robustness to implement a 12-bit delta-sigma ADC for monitoring bias signals instead of the common SAR solution, which requires a calibration circuit for such level of resolution. However, delta-sigma converters are not suitable to measure DC signals. Instead it was used an incremental delta-sigma converter, which can be considered a delta-sigma data converter in transient mode, because it can be reset and easily multiplexed among several channels. The presented ADC is implemented inside TimePix4 and its purpose is to monitor 32 internal bias voltages. These are DC signals, so a sampling rate of 1ksample/s as much is needed. The chip has been designed in a 65nm CMOS process, and it will be submitted for fabrication during 2019.
The design of the ADC started by working at architectural level with Matlab. This allowed to determine the oversampling ratio, the open gain and band-width of the operational amplifiers, as well as to dimension the sizes of the capacitors. Instead of creating Simulink models for each integrating stage, it was used the SimSides library for Matlab developed by INM-CNM to design delta-sigma converters. It was found that a second order Cascaded Integrators Feed Forward (CIFF) architecture operating with an oversampling rate of 210 allowed to meet the requirements in terms of conversion speed, area and power consumption.
The phases of the first integrator stage were modified in order to work with single-ended input signals and provide a fully differential output for the fully differential second stage. The operational amplifiers are fully differential folded cascode with a switched-capacitor circuit to generate the common-mode voltage. With the 65nm process, it was not possible to reach an open-loop gain of at least of 75dB as needed, so gain-boosting techniques were used to enhance the gain to 90dB. The power consumption of the converter at an operating oversampling frequency of 250kHz is of 8µW working at 1.2V. A lot of care was taken in the layout to avoid crosstalk between signals that could degrade the performances of the ADC. The size of the layout of the modulator is of 110x150µm2.
The correct operation of the ADC was tested by simulating the converter in free-running mode, that is, as a conventional delta-sigma converter. In incremental mode, the test of the whole range would have required a week at schematic level, so we only tested some small regions of the whole range for all corners at schematic and layout level. Results shown that ADC achieved the desired resolution for an input range of 25mV-1175mV. For the free-running test mode, it was obtained a SNR 84.9dB for the given input range in the typical case.
