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Description
This paper presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 4 ps, fabricated in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. To achieve the low resolution, the delay elements are implemented using a new interlocked interpolation technique to reduce the Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) error. The delay line is placed inside a Delay Locked Look (DLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation.
Summary
Time-to-Digital Converters (TDCs) can be compared to Analog-to-Digital Converters (ADCs) as they digitize analog-like time differences instead of analog voltage differences. Several applications require precise time measurements such as particle tracking in high energy physics, where a high resolution TDC is required to distinguish tracks from different vertices. Also inside Time-Of-Flight distance measurements and many other circuits like frequency synthesizers, clock generators, clock data recovery circuits (CDRs), time-domain ADCs and jitter measurement circuits, the on-board TDC is critical to the overall performance of the circuit. High-performance TDCs thus require a small quantization delay, low noise, large sampling speed and high linearity. One of the main challenges for increasing the resolution of the TDC, is overcoming the minimum gate- delay of the technology. The methods which are commonly used to overcome this problem are, the Vernier architecture, (passive or active) interpolation and the parallel TDC. All of these architectures come with their own challenges, but the most suitable architecture for the mentioned applications is the passive interpolation.
In this design the Delay Line (DL) consists of 64 pseudo-differential delay cells which are interpolated four times, this results in a resolution of 4 ps. Increasing the number of interpolation stages will also increase the raw resolution, but the nonlinear behavior of the passive interpolation will cause the DNL and INL error to dominate the effective resolution. Therefore, an interpolation of only four times has been chosen. To further improve the performance of the TDC, a new technique of interlocked interpolation is proposed. Hereby two delay lines are connected through each other by the interpolation resistors. Therefore, interlocking the phase of every second interpolation node. By using this technique, the DNL and INL error decreases significantly. The TDC is designed to be tolerant to ionizing radiation up to 2 MGy. In order to achieve MGy TID tolerance enclosed layout transistors are used. Additionally, the DL is placed in a Delay Locked Loop (DLL) to ensure that the TDC is robust against Process, Voltage and Temperature (PVT) variations, and to ionizing radiation.
