Speaker
Description
CaRIBOu is a flexible data acquisition system for prototyping silicon pixel detectors. The core of the system consists of the Control and Readout (CaR) board, a versatile module providing the hardware environment for various target ASICs, including powering and slow-control infrastructure and high-speed full-duplex GTx links up to 12.5 Gbps. The CaR board connects to a Zynq system-on-chip board, which runs a fully featured Yocto-based Linux and a data acquisition framework (Peary). Using the CaRIBOu system significantly reduces the time required to test and debug detector prototypes by providing ready-to-use peripheries and re-useable software interfaces for a variety of detectors.
Summary
Developing new detectors requires the design of an adequate readout and control system. Such a system typically consist of hardware in form of a readout board containing programmable logic to provide an interface to the chip, power supplies for biasing the detector chip, as well as DACs and ADCs for setting and measuring operation parameters, generating test pulses, etc. One also needs to write software for controlling the detector and hardware peripherals and for data readout. This process needs to be repeated for each new chip developed, which requires different voltage levels or different number of data lines. The CaRIBOu system, on the other hand, provides a robust, versatile DAQ system, which can be easily adjusted to the needs of different detectors. Using such a system therefore saves development cost and reduces the time needed to get first data from the detector. CaRIBOu is a combination of hardware and software modules that forms a stand-alone readout and DAQ system for detector prototypes. It was initially developed for testing newly developed pixel-detector chips for ATLAS and for a future CLIC detector. Adding support for a new chip is a matter of writing a piece of code performing an interface between the chip-specific features and the standard data and control interface of the CaRIBOu system. The system is based on a Xilinx Zynq System-on-Chip (SoC) architecture combining the power of a programmable hardware (FPGA) and a full Linux operating system allowing to run software in a high-level programming language. It can run either stand-alone, storing data to a local filesystem, or connected via network interface to a data storage or a superior control system. The data decoding and analysis can be done either directly in the system both in software and in FPGA-based hardware, or the data can be stored in a raw format and analysed offline.
The talk presents the structure and capabilities of the DAQ system and shows example applications and future plans.
