Speaker
Description
The pixel-strip modules for the CMS Tracker Phase Two Upgrade for the HL-LHC integrate a readout hybrid (PS-ROH) for the control and data acquisition link. This hybrid is based on the new, low power and compact gigabit transceiver (lpGBT) and the Versatile Transceiver VTRx+ specifically designed for the upgrade. A characterization board was first designed to qualify the design rules and the achievable timing performance of the gigabit block. This design enabled the development of the PS-ROH hybrid for the CMS Tracker PS modules. A testing setup was also developed to verify the PS-ROH performance before its integration in modules.
Summary
Two new front-end module types (2S and PS) are currently under development for the Compact Muon Solenoid (CMS) Tracker Phase Two Upgrade for the High Luminosity Large Hadron Collider (HL-LHC). These 2S modules on a double strip-strip (2S) sensor configuration with an active area of 10 × 10 cm2. The PS modules contain a strip sensor and a macro pixelated strip sensor of 5 × 10 cm2 and two front-end hybrids interconnected with a power hybrid and with an optical readout hybrid. The readout hybrid enables the optical transmission of clock, control and data at transmission speeds up to 10.24 Gbps in the cold and radiation environment of the tracker.
The optical readout hybrid interfaces the two front-end hybrids with the new low power gigabit transceiver lpGBT. This new ball grid array chip provides various operation modes, high-speed differential ports (e-links), digital input and output control ports and eight analog to digital converter inputs. It provides an enhanced clock distribution and phase alignment features.
A characterization board enabling all possible configurations was designed in the first step on a six layers rigid printed circuit board. It provides 100 Ω matched impedance routing with test connectors for lpGBT Phase Shifted Clocks, some of the e-links and with high data rate SMA connectors to interface with an external optical module (VTRx+). The differential pair topologies were verified with signal integrity simulations. Two decoupling scheme configurations on the top and on the bottom layer are proposed and were characterized by power integrity simulations. This board is in production and will be tested in May 2019.
The lpGBT was later on integrated into the PS-ROH, on a four layers flexible circuit. Suitable differential topologies were defined for an achievable impedance of 90 Ω for the e-links. A specific differential pair topology for the gigabit lines connecting to the VTRx+ was also defined. The decoupling scheme is here only possible on the top layer, and power integrity simulations allowed comparing the expected performance with respect to the characterization board implementation. This board is also under production and will be tested in July 2019.
The performance of the characterization boards will be measured with laboratory instrumentation. However, because the PS-ROH is a tracker specific integration, a dedicated test bench is under development and will be assembled in June 2019. This specific infrastructure allows verifying the PS-ROH performance; it can be scaled in a multiplexed testing infrastructure for production phase quality control tests.
The proceeding will present the design parameters for rigid and flexible circuit integrations, the optimal differential pair implementations, and the data transmission properties. The PS-ROH implementation on a flexible circuit and the testing method are proposed as an application example.
