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Design of a low-noise, high-linearity, readout ASIC for CdZnTe detectors in gamma spectrometers

Dec 14, 2019, 2:52 PM
1m
POSTER - Sun: B1F-Meeting room#3, B2F-RAN1/2; Mon-Wed: B1F Meeting rooms #5-6 (International Conference Center Hiroshima)

POSTER - Sun: B1F-Meeting room#3, B2F-RAN1/2; Mon-Wed: B1F Meeting rooms #5-6

International Conference Center Hiroshima

Peace Memorial Park, Hiroshima-shi
POSTER ASICs POSTER

Speaker

Dr Jia Wang (Northwestern Polytechnical University)

Description

CdZnTe detectors are promising candidates for X-ray and gamma ray detecting, due to their good energy resolution, high detection efficiency and room temperature operation. They are suitable to be equipped in gamma spectrometers for energy measurement. Compared to board system, application specific integrated circuit (ASIC) features lower power consumption and smaller size. Especially for portable gamma spectrometer, readout ASIC is necessary. Low noise is required in order to improve energy resolution. Since the CdZnTe detectors may be far away from the ASIC, the influence of input capacitance is also hoped to be low. In order to measure energy in a large range, the output voltage must be always linear. Therefore, the gain of shaper is restricted. Tradeoff should be considered between noise and linearity.
The presented work aims to achieving low-noise and high-linearity in a wide range of input charge. In order to improve linearity, an active resistor and a high-linear analog buffer are employed. A $CR-(RC)^2$ shaper is proposed. Different types of resistances are utilized in the first stage and second stage of the shaper, to achieve low noise and high linearity at the same time. A channel of the proposed circuit is composed of a preamplifier, a shaper, a peak and hold circuit, which can automatically detect the peak of shaper output voltage. The output voltage is not read out, except a channel is hit. Therefore, power consumption is decreased.
A prototype chip with 8 channels has been designed and fabricated in a standard commercial 1P6M 0.18 $\mu$m CMOS process. Die area of one channel is about 650 $\mu$m $\times$ 110 $\mu$m. The input charge range is from 1.5 fC to 60 fC. Peaking time can be adapted from 3 $\mu$s to 5 $\mu$s. Measured ENC is about 206 $e^-$ at input capacitor of 0 F with the slop of 8.1 $e^-$/pF. The gain is 18.7 mV/fC at peaking time of 4 $\mu$s. Non-linearity is about 3%. More measured results will be presented in this symposium.

Submission declaration Original and unpublished

Primary authors

Dr Jia Wang (Northwestern Polytechnical University) Mr Xuan Luo (Northwestern Polytechnical University) Dr Ran Zheng (Northwestern Polytechnical University) Dr Xiaomin Wei (Northwestern Polytechnical University) Prof. Changqing Feng (University of Science and Technology of China) Prof. Yann Hu (University of Strasbourg)

Presentation materials