Indico has been upgraded to version 3.1. Details in the SSB

Development of Front-end ASIC for Silicon-strip Detectors of J-PARC Muon g-2/EDM Experiment

Dec 14, 2019, 2:54 PM
1m
POSTER - Sun: B1F-Meeting room#3, B2F-RAN1/2; Mon-Wed: B1F Meeting rooms #5-6 (International Conference Center Hiroshima)

POSTER - Sun: B1F-Meeting room#3, B2F-RAN1/2; Mon-Wed: B1F Meeting rooms #5-6

International Conference Center Hiroshima

Peace Memorial Park, Hiroshima-shi
POSTER ASICs POSTER

Speaker

Dr Yutaro Sato (High Energy Accelerator Research Organization)

Description

We develop a front-end ASIC for the silicon strip detector of the J-PARC muon g-2/EDM experiment, which aims to measure the muon anomalous magnetic moment and electric dipole moment to search for new physics beyond the Standard Model. In this experiment, we use a silicon strip detector with high granularity and fast response to detect positrons from muon decay. Since the timing of the muon decay is key information in the experiment, the ASIC is required to tolerate a high hit rate of 1.4 MHz per strip and to be stable to the change of hit rate by a factor of 1/150. To accommodate the pulsed muon beam at J-PARC, the ASIC has a buffer memory to save the binary hit information.
The prototype ASIC has been designed and fabricated using the Silterra 180 ns CMOS process. The prototype contains 128 readout channels, consisting each of a charge-sensitive-amplifier, a CR-RC shaper, a differentiator, two comparators and the buffer memory. Threshold voltage at comparators are adjustable channel by channel using 6-bit Digital-to-Analog Converter (DAC) to compensate channel-to-channel threshold variations. The output of the comparators is then sampled by a 200 MHz clock for the period of 40.96 us and are saved in the buffer memory. The data is serially readout before the next bunch arrives. The main difference of the previous prototype is to add the differentiator at the output of the CR-RC shaper to reduce the time-walk effect. Several bias parameters in the analog circuit are optimized to improve the performance of the noise and peaking time.
The fabricated prototype was directly mounted on a printed circuit board for the evaluation test and was electrically connected by wire-bonding. We checked the response of the prototype with the test pulse charge and estimated the gain, equivalent noise charge, pulse width, time-walk and timing-jitter. In this talk, we present the design of the front-end ASIC and its performance.

Submission declaration Original and unpublished

Primary authors

Dr Eitaro Hamada (High Energy Accelerator Research Organization) Dr Junji Tojo (Kyushu University) Dr Manobu Tanaka (High Energy Accelerator Research Organization) Dr Masayoshi Shoji (High Energy Accelerator Research Organization) Dr Osamu Sasaki (High Energy Accelerator Research Organization) Dr Taikan Suehara (Kyushu University) Dr Takashi Yamanaka (Kyushu University) Dr Tamaki Yoshioka (Kyushu University) Dr Tetsuichi Kishishita (High Energy Accelerator Research Organization) Dr Tsutomu Mibe (High Energy Accelerator Research Organization) Dr Yowichi Fujita (High Energy Accelerator Research Organization) Mr Yuki Tsutsumi (Kyushu University) Dr Yutaro Sato (High Energy Accelerator Research Organization)

Presentation materials