28 July 2020 to 6 August 2020
virtual conference
Europe/Prague timezone

A muon tracking algorithm for Level 1 trigger in the CMS barrel muon chambers during HL-LHC

29 Jul 2020, 13:30
3m
virtual conference

virtual conference

Poster 13. Detectors for Future Facilities (incl. HL-LHC), R&D, Novel Techniques Detectors for Future Facilities (incl. HL-LHC), R&D, Novel Techniques - Posters

Speaker

Jaime Leon Holgado (CIEMAT, Spain)

Description

The electronics of the CMS (Compact Muon Solenoid) DT (Drift Tubes) chambers will need to be replaced for the HL-LHC (High Luminosity Large Hadron Collider) operation due to the increase of occupancy and trigger rates in the detector, which cannot be sustained by present system. A system is being designed that will forward asynchronously the totality of the chambers signals to the control room, at full resolution. A new backend system will be in charge of building the trigger primitives of each chamber out of this asynchronous information, aiming at achieving resolutions comparable to the ones that the offline High Level Trigger can obtain nowadays. In this way, the new system will provide improved functionality with respect to present system, allowing to improve the resilience to potential aging situations. An algorithm for the trigger primitive generation that will run in this new backend system has been developed and implemented in firmware. The performance of this algorithm has been validated through different methods: from a software emulation approach to hardware implementation tests. The performance obtained is very good, with optimal timing and position resolutions, close to the ultimate performance of the DT chamber system. One important validation step has included the implementation of this algorithm in a prototype chain of the HL-LHC electronics, which has been operated with real DT chambers under cosmic data taking campaigns. The new trigger primitive generation has been implemented in the so-called AB7, spare uTCA boards from present DT system which host Xilinx Virtex 7 FPGAs. The performance of this prototyping system has been verified and will be presented in this contribution, showing the goodness of the design for the expected functionality during HL-LHC.

Secondary track (number) 12.

Primary author

Jaime Leon Holgado (CIEMAT, Spain)

Presentation Materials