28 July 2020 to 6 August 2020
virtual conference
Europe/Prague timezone

The LHCb VELO Upgrade Programme for High Luminosity running at the LHC and HL-LHC

28 Jul 2020, 16:15
virtual conference

virtual conference

Talk 13. Detectors for Future Facilities (incl. HL-LHC), R&D, Novel Techniques Detectors for Future Facilities (incl. HL-LHC), R&D, Novel Techniques


Timothy David Evans (CERN)


The detector currently under construction is designed to run throughout Run 3 and 4, after which a further major Upgrade will be implemented to enable the LHCb Upgrade II physics goals. The Upgrade II detector is designed to run at instantaneous luminosities of 2 × $10^{34}cm^{-2}s^{-1}$, an order of magnitude above Upgrade I, and accumulate a sample of more than 300 fb-1. At this intensity, the mean number of visible proton- proton interactions per crossing would be 56, producing around 2500 charged particles within the LHCb acceptance. The Upgrade II programme is reliant on an efficient and precise vertex detector (VELO). This subdetector enables real time reconstruction of tracks from all LHC bunch crossings in the software trigger system. The Upgrade II luminosity poses significant challenges which necessitate the construction of a new VELO with enhanced capabilities. Compared to Upgrade I there will be a further order of magnitude increase in data output rates accompanied by corresponding increases in radiation levels and occupancies. To cope with the large increase in pile-up, new techniques to assign correctly each b hadron to the primary vertex from which it originates, and to address the challenge of real time pattern recognition, are needed. These challenges will be met by the development of a new 4D hybrid pixel detector with enhanced rate and timing capabilities in the ASIC and sensor. Improvements in the mechanical design of the Ugrade II VELO will also be needed to allow for periodic module replacement. The design will be further optimised to minimise the material before the first measured point on a track (which is dominated by the secondary vacuum enclosure) and to achieve a more fully integrated module design with thinned sensors and ASICs combined with a lightweight cooling solution. It is envisaged that the readout ASIC will follow the VeloPix /Timepix4 development path with a novel design will including in-pixel timing and calibration, allowing the pixel time stamps to reach a precision of 10s of picoseconds, and a new custom output serialiser will be included. The R&D programme will explore the capabilities of combining fast timing information with small pixel size, and examine clock distribution issues for fine timing over a full system. The capabilities of the sensor to deliver fast timing will be explored for different sensor designs. The needs of the Upgrade II VELO will be outlined, along with the R&D steps envisaged to achieve the goal of a 4D pixel tracker.

Secondary track (number) 12

Primary author

Presentation Materials