16–18 Feb 2021
FBK, Trento
Europe/Zurich timezone

Optimization of the 65 nm CMOS Linear front-end circuit for the CMS pixel readout at the HL-LHC

17 Feb 2021, 14:20
20m
FBK, Trento

FBK, Trento

Oral Electronics Session 7: Electronics

Speaker

Luigi Gaioni (INFN - National Institute for Nuclear Physics)

Description

A prototype chip integrating a matrix of 16 × 16 readout channels has been designed and tested in the framework of the RD53 developments for pixel detectors at the High-Luminosity LHC. The matrix is divided in two regions featuring different flavours of the front-end stage, or Linear front-end, that have been tested and compared. The front-end channels include a low-noise charge sensitive amplifier with detector leakage compensation circuit, a free-running comparator, and a current-mode DAC for threshold tuning. The front-end circuits were developed in a 65 nm CMOS technology and feature an overall area of 35 μm × 35 μm with a current consumption close to 5 μA. The prototype has been tested before and after exposure to total ionizing doses up to 1 Grad(SiO$_2$) of X-rays. A comprehensive discussion of the design and of the characterization of the readout channels will be provided in the conference paper.

Primary authors

Luigi Gaioni (INFN - National Institute for Nuclear Physics) Massimo Manghisoni (Università di Bergamo - Italy) Lodovico Ratti (University of Pavia) Valerio Re (INFN) Elisa Riceputi (University of Bergamo) Gianluca Traversi (University of Bergamo) Dr Giulio Dellacasa (INFN Torino (IT)) Lino Demaria (Universita e INFN Torino (IT)) Sara Garbolino (Universita e INFN Torino (IT)) Ennio Monteil (Universita e INFN Torino (IT)) Francesco Rotondo (Universita e INFN Torino (IT))

Presentation materials