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Description
The aim of this work is to develop an internal PLL for ASIC developments which integrates time measurement or which requires an internal clock in the range of GigaHertz. For future upgrades in High Energy Physic detectors experiments, time measurement becomes a decisive element, which will make it possible to reduce the data flow and improve the spatial accuracy of the interaction point. This design is based on a top down design methodology including a behavioural and a linearized PLL. Two PLLs were designed with two different VCOs based on ring and LC tank oscillator.
Summary (500 words)
Introduction:
Two PLLs were designed to evaluate the jitter performance and the silicon area required. The first PLL implements a ring oscillator architecture. Integrated PLLs use ring oscillator as VCO for lower silicon area. However, the low damping factor (at most equal to π/2) of these oscillators permits to achieve few ps rms PLL jitter. The second one uses a LC oscillator for its higher Q factor. VCO based on LC tank oscillator have damping factors greater than 10, which results in ultra-low jitter PLLs. A Verilog-A model PLL and a linearized one was designed to scale intrinsic jitter of each block and stability.
Architecture:
The block diagram of a PLL operating as a clock generator is shown in figure 1. It consists of a frequency reference input (Fref), a phase/frequency detector (PFD), a charge pump (CP) with its output current (Icp), a low pass loop filter (LF) with its equivalent impedance (Zlp), a voltage controlled oscillator (VCO) with its conversion gain (Kvco) and a frequency divider (FD) with its divider ratio (N). The feedback loop acts to equal in phase Fref (40 MHz) and Ffb. When the PLL is locked, the frequency at the output is 2.56 GHz.
Test results:
The bandwidth of the output driver is limited to 1.5 GHz and the maximum output divider frequency recordable is 1.28 GHz. For the two PLLs, one can plot the output phase noise in dBc/Hz from 40 MHz to 1.28 GHz (figure 2 and 3). As predicted, all the curves are separately by 6 dB. For both PLLs, some peaks at frequencies multiple of 40 MHz are observed. For the specific case of the ring oscillator PLL, additional peaks at frequencies not multiple of 40 MHz are present. A peak in phase noise plot at 12 MHz is observed in figure 2. This frequency is an alias of the frequency of the standalone VCO divided output (628 MHz, cf figure 2). The final absolute jitter at 1.28 GHz in ps rms is evaluated from the phase noise plots and extrapolated for 2.56 GHz output. The absolute jitter are respectively 2.05 ps rms for the ring oscillator PLL and 1.6 ps rms for the LC tank oscillator PLL. Offline analysis at 1.28 GHz for the two PLLs allows to plot the absolute output jitter (figure 4 and 5) as a function of the offset frequency carrier. This two set of curves are well in accordance.
Conclusion:
We have designed two low jitter PLLs using a top down methodology. A Verilog-A behavioural PLL has been qualified in terms of jitter for all blocks of the PLLs. The absolute output jitter calculated from the phase noise plots are 2.05 ps rms for the ring oscillator architecture and 1.6 ps rms for the LC tank oscillator.
Possible improvements are reducing internal couplings, optimizing VCOs jitter and therefore minimizing output PLL jitter. Ring oscillator with Injection locked architecture is a promising way of improvement.
